arm/mm/proc-feroceon.S

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  *  linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon
5  *  Heavily based on proc-arm926.S
14 #include <asm/pgtable-hwdef.h>
17 #include "proc-macros.S"
20  * This is the maximum size of an area which will be invalidated
22  * than this, and we go for the whole cache.
30  * the cache line size of the I and D cache
47 	mrc	p15, 0, r0, c0, c0, 1		@ read cache type register
51 	mov	r0, r0, lsr #18			@ get cache size order
52 	movne	r3, #((4 - 1) << 30)		@ 4-way
54 	moveq	r3, #0				@ 1-way
55 	mov	r2, r2, lsl r0			@ actual cache size
91 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
94 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
123 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
130  *	Clean and invalidate all cache entries in a particular
140  *	Clean and invalidate the entire cache.
149 2:	mcr	p15, 0, ip, c7, c14, 2		@ clean + invalidate D set/way
157 	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
164  *	Clean and invalidate a range of cache entries in the
167  *	- start	- start address (inclusive)
168  *	- end	- end address (exclusive)
169  *	- flags	- vm_flags describing address space
173 	sub	r3, r1, r0			@ calculate total size
177 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
180 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
194  *	region described by start, end.  If you have non-snooping
197  *	- start	- virtual start address
198  *	- end	- virtual end address
208  *	region described by start, end.  If you have non-snooping
211  *	- start	- virtual start address
212  *	- end	- virtual end address
215 	bic	r0, r0, #CACHE_DLINESIZE - 1
216 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
226  *	flush_kern_dcache_area(void *addr, size_t size)
228  *	Ensure no D cache aliasing occurs, either with itself or
229  *	the I cache
231  *	- addr	- kernel address
232  *	- size	- region size
237 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
242 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
249 	add	r1, r0, #PAGE_SZ - CACHE_DLINESIZE	@ top addr is inclusive
252 	mcr	p15, 5, r0, c15, c15, 0		@ D clean/inv range start
253 	mcr	p15, 5, r1, c15, c15, 1		@ D clean/inv range top
256 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
265  *	are not cache line aligned, those lines must be written
268  *	- start	- virtual start address
269  *	- end	- virtual end address
275 	tst	r0, #CACHE_DLINESIZE - 1
276 	bic	r0, r0, #CACHE_DLINESIZE - 1
277 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
278 	tst	r1, #CACHE_DLINESIZE - 1
279 	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
280 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
290 	tst	r0, #CACHE_DLINESIZE - 1
291 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
292 	tst	r1, #CACHE_DLINESIZE - 1
293 	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
298 	mcr	p15, 5, r0, c15, c14, 0		@ D inv range start
299 	mcr	p15, 5, r1, c15, c14, 1		@ D inv range top
308  *	- start	- virtual start address
309  *	- end	- virtual end address
315 	bic	r0, r0, #CACHE_DLINESIZE - 1
316 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
330 	mcr	p15, 5, r0, c15, c13, 0		@ D clean range start
331 	mcr	p15, 5, r1, c15, c13, 1		@ D clean range top
341  *	- start	- virtual start address
342  *	- end	- virtual end address
346 	bic	r0, r0, #CACHE_DLINESIZE - 1
347 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
361 	mcr	p15, 5, r0, c15, c15, 0		@ D clean/inv range start
362 	mcr	p15, 5, r1, c15, c15, 1		@ D clean/inv range top
368  *	dma_map_area(start, size, dir)
369  *	- start	- kernel virtual start address
370  *	- size	- size of region
371  *	- dir	- DMA direction
382  *	dma_map_area(start, size, dir)
383  *	- start	- kernel virtual start address
384  *	- size	- size of region
385  *	- dir	- DMA direction
396  *	dma_unmap_area(start, size, dir)
397  *	- start	- kernel virtual start address
398  *	- size	- size of region
399  *	- dir	- DMA direction
408 	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
418  * Most of the cache functions are unchanged for this case.
439 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
475 	mcreq	p15, 0, ip, c7, c5, 0		@ invalidate I cache
479 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
495 	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
504 /* Suspend/resume support: taken from arch/arm/mm/proc-arm926.S */
509 	stmfd	sp!, {r4 - r6, lr}
513 	stmia	r0, {r4 - r6}
514 	ldmfd	sp!, {r4 - r6, pc}
519 	mcr	p15, 0, ip, c8, c7, 0	@ invalidate I+D TLBs
520 	mcr	p15, 0, ip, c7, c7, 0	@ invalidate I+D caches
521 	ldmia	r0, {r4 - r6}
533 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
536 	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
545 	.size	__feroceon_setup, . - __feroceon_setup
560 	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
568 	string	cpu_88fr531_name, "Feroceon 88FR531-vd"
569 	string	cpu_88fr571_name, "Feroceon 88FR571-vd"
576 .macro feroceon_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache:req
599 	.long	\cache
600 	 .size	__\name\()_proc_info, . - __\name\()_proc_info
605 		cpu_name=cpu_feroceon_name, cache=feroceon_cache_fns
609 		cache=feroceon_cache_fns
611 		cache=feroceon_range_cache_fns
613 		cache=feroceon_range_cache_fns