arm/mm/proc-arm925.S

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8  *  Copyright (C) 2002-2003 MontaVista Software, Inc.
10  *  Update for Linux-2.6 and cache flush improvements
13  *  hacked for non-paged-MM by Hyok S. Choi, 2004.
15  * These are the low level assembler for performing cache and TLB
18  *  CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
20  * Some additional notes based on deciphering the TI TRM on OMAP-5910:
22  * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
24  *	  at once. This is the default value. See TRM 2-20 and 2-24 for
27  * NOTE2: Default is the "D-cache clean and flush entry mode". It looks
28  *	  like the "Transparent mode" must be on for partial cache flushes
29  *	  to work in this mode. This mode only works with 16-bit external
30  *	  memory. See TRM 2-24 for more information.
32  * NOTE3: Write-back cache flushing seems to be flakey with devices using
34  *        write-through cache with CONFIG_CPU_DCACHE_WRITETHROUGH (this is
35  *        the default for OMAP-1510).
43 #include <asm/pgtable-hwdef.h>
46 #include "proc-macros.S"
49  * The size of one data cache line.
54  * The number of data cache segments.
59  * The number of lines in a cache segment.
64  * This is the size at which it becomes more efficient to
65  * clean the whole cache, rather than using the individual
66  * cache line maintenance instructions.
109 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
112 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
131 	mcr	p15, 0, r2, c1, c0, 0		@ Disable I cache
143 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
150  *	Clean and invalidate all cache entries in a particular
159  *	Clean and invalidate the entire cache.
166 	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
169 	mov	r3, #(CACHE_DENTRIES - 1) << 4	@ 256 entries in segment
170 2:	mcr	p15, 0, r3, c7, c14, 2		@ clean+invalidate D index
175 	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
182  *	Clean and invalidate a range of cache entries in the
185  *	- start	- start address (inclusive)
186  *	- end	- end address (exclusive)
187  *	- flags	- vm_flags describing address space
191 	sub	r3, r1, r0			@ calculate total size
196 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
199 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
203 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
206 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
220  *	region described by start, end.  If you have non-snooping
223  *	- start	- virtual start address
224  *	- end	- virtual end address
233  *	region described by start, end.  If you have non-snooping
236  *	- start	- virtual start address
237  *	- end	- virtual end address
240 	bic	r0, r0, #CACHE_DLINESIZE - 1
241 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
251  *	flush_kern_dcache_area(void *addr, size_t size)
253  *	Ensure no D cache aliasing occurs, either with itself or
254  *	the I cache
256  *	- addr	- kernel address
257  *	- size	- region size
261 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
266 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
275  *	are not cache line aligned, those lines must be written
278  *	- start	- virtual start address
279  *	- end	- virtual end address
285 	tst	r0, #CACHE_DLINESIZE - 1
286 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
287 	tst	r1, #CACHE_DLINESIZE - 1
288 	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
290 	bic	r0, r0, #CACHE_DLINESIZE - 1
291 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
303  *	- start	- virtual start address
304  *	- end	- virtual end address
310 	bic	r0, r0, #CACHE_DLINESIZE - 1
311 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
324  *	- start	- virtual start address
325  *	- end	- virtual end address
328 	bic	r0, r0, #CACHE_DLINESIZE - 1
331 	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
333 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
342  *	dma_map_area(start, size, dir)
343  *	- start	- kernel virtual start address
344  *	- size	- size of region
345  *	- dir	- DMA direction
356  *	dma_unmap_area(start, size, dir)
357  *	- start	- kernel virtual start address
358  *	- size	- size of region
359  *	- dir	- DMA direction
368 	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
373 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
395 	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
398 	mov	r3, #(CACHE_DENTRIES - 1) << 4	@ 256 entries in segment
399 2:	mcr	p15, 0, r3, c7, c14, 2		@ clean & invalidate D index
403 	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
406 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
421 	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
431 	/* Transparent on, D-cache clean & flush mode. See  NOTE2 above */
436 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
439 	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
443 	mov	r0, #4				@ disable write-back on caches explicitly
456 	.size	__arm925_setup, . - __arm925_setup
469 	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
482 .macro arm925_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache  argument
505 	.size	__\name\()_proc_info, . - __\name\()_proc_info