arm/mm/context.c

1 // SPDX-License-Identifier: GPL-2.0-only
5  *  Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved.
20 #include <asm/proc-fns.h>
26  * +-------------------------+-----------+
28  * +-------------------------+-----------+
30  * +-------------------------------------+
37  * by non-64-bit operations.
59 	context_id = mm->context.id.counter;  in a15_erratum_get_cpumask()
80  * no need for a reserved set of tables (the active ASID tracking prevents
81  * any issues across a rollover).
94 	"	mrc	p15, 0, %0, c2, c0, 1		@ read TTBR1\n"  in cpu_set_reserved_ttbr0()
112 	pid = task_pid_nr(thread->task) << ASID_BITS;  in contextidr_notifier()
147 		 * rollover, but hasn't run another task in  in flush_context()
158 	/* Queue a TLB invalidate and flush the I-cache if necessary. */  in flush_context()
192 	u64 asid = atomic64_read(&mm->context.id);  in new_context()
199 		 * If our current ASID was active during a rollover, we  in new_context()
206 		 * We had a valid ASID in a previous life, so try to re-use  in new_context()
220 	 * overlapping level-1 descriptors used to map both the module  in new_context()
243 	if (unlikely(mm->context.vmalloc_seq != init_mm.context.vmalloc_seq))  in check_and_switch_context()
253 	asid = atomic64_read(&mm->context.id);  in check_and_switch_context()
260 	asid = atomic64_read(&mm->context.id);  in check_and_switch_context()
263 		atomic64_set(&mm->context.id, asid);  in check_and_switch_context()
276 	cpu_switch_mm(mm->pgd, mm);  in check_and_switch_context()