arm/mm/cache-v4wb.S

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  *  linux/arch/arm/mm/cache-v4wb.S
5  *  Copyright (C) 1997-2002 Russell king
12 #include "proc-macros.S"
15  * The size of one data cache line.
20  * The total size of the data cache.
27 # error Unknown cache size
31  * This is the size at which it becomes more efficient to
32  * clean the whole cache, rather than using the individual
33  * cache line maintenance instructions.
35  *  Size  Clean (ticks) Dirty (ticks)
39  *  32768  150 149 150   214 216 212 <---
42  *  Whole  132 136 132   221 217 207 <---
59 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
66  *	Clean and invalidate all cache entries in a particular address
74  *	Clean and invalidate the entire cache.
78 	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
89 	add	r2, r2, #FLUSH_BASE_MINICACHE - FLUSH_BASE
101  *	Invalidate a range of cache entries in the specified
104  *	- start - start address (inclusive, page aligned)
105  *	- end	- end address (exclusive, page aligned)
106  *	- flags	- vma_area_struct flags describing address space
110 	sub	r3, r1, r0			@ calculate total size
112 	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
114 	cmp	r3, #CACHE_DLIMIT		@ total size >= limit?
115 	bhs	__flush_whole_cache		@ flush whole D cache
117 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
118 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
127  *	flush_kern_dcache_area(void *addr, size_t size)
129  *	Ensure no D cache aliasing occurs, either with itself or
130  *	the I cache
132  *	- addr	- kernel address
133  *	- size	- region size
143  *	region described by start.  If you have non-snooping
146  *	- start  - virtual start address
147  *	- end	 - virtual end address
156  *	region described by start.  If you have non-snooping
159  *	- start  - virtual start address
160  *	- end	 - virtual end address
163 	bic	r0, r0, #CACHE_DLINESIZE - 1
164 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
165 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
170 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
180  *	are not cache line aligned, those lines must be written
183  *	- start  - virtual start address
184  *	- end	 - virtual end address
187 	tst	r0, #CACHE_DLINESIZE - 1
188 	bic	r0, r0, #CACHE_DLINESIZE - 1
189 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
190 	tst	r1, #CACHE_DLINESIZE - 1
191 	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
192 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
204  *	- start  - virtual start address
205  *	- end	 - virtual end address
208 	bic	r0, r0, #CACHE_DLINESIZE - 1
209 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
221  *	- start  - virtual start address
222  *	- end	 - virtual end address
230  *	dma_map_area(start, size, dir)
231  *	- start	- kernel virtual start address
232  *	- size	- size of region
233  *	- dir	- DMA direction
244  *	dma_unmap_area(start, size, dir)
245  *	- start	- kernel virtual start address
246  *	- size	- size of region
247  *	- dir	- DMA direction
258 	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)