arm/mach-u300/core.c

29 #define U300_NAND_CS0_PHYS_BASE		0x80000000
31 #define U300_NAND_IF_PHYS_BASE		0x9f800000
36 #define U300_AHB_PER_PHYS_BASE		0xa0000000
37 #define U300_AHB_PER_VIRT_BASE		0xff010000
39 #define U300_FAST_PER_PHYS_BASE		0xc0000000
40 #define U300_FAST_PER_VIRT_BASE		0xff020000
42 #define U300_SLOW_PER_PHYS_BASE		0xc0010000
43 #define U300_SLOW_PER_VIRT_BASE		0xff000000
45 #define U300_BOOTROM_PHYS_BASE		0xffff0000
46 #define U300_BOOTROM_VIRT_BASE		0xffff0000
48 #define U300_SEMI_CONFIG_BASE		0x2FFE0000
55 #define U300_AHB_BRIDGE_BASE		(U300_AHB_PER_PHYS_BASE+0x0000)
56 /* Vectored Interrupt Controller 0, servicing 32 interrupts */
57 #define U300_INTCON0_BASE		(U300_AHB_PER_PHYS_BASE+0x1000)
58 #define U300_INTCON0_VBASE		IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
60 #define U300_INTCON1_BASE		(U300_AHB_PER_PHYS_BASE+0x2000)
61 #define U300_INTCON1_VBASE		IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
63 #define U300_MSPRO_BASE			(U300_AHB_PER_PHYS_BASE+0x3000)
65 #define U300_EMIF_CFG_BASE		(U300_AHB_PER_PHYS_BASE+0x4000)
72 #define U300_FAST_BRIDGE_BASE		(U300_FAST_PER_PHYS_BASE+0x0000)
74 #define U300_MMCSD_BASE			(U300_FAST_PER_PHYS_BASE+0x1000)
76 #define U300_PCM_I2S0_BASE		(U300_FAST_PER_PHYS_BASE+0x2000)
78 #define U300_PCM_I2S1_BASE		(U300_FAST_PER_PHYS_BASE+0x3000)
80 #define U300_I2C0_BASE			(U300_FAST_PER_PHYS_BASE+0x4000)
82 #define U300_I2C1_BASE			(U300_FAST_PER_PHYS_BASE+0x5000)
84 #define U300_SPI_BASE			(U300_FAST_PER_PHYS_BASE+0x6000)
86 #define U300_UART1_BASE			(U300_FAST_PER_PHYS_BASE+0x7000)
95 #define U300_SYSCON_BASE		(U300_SLOW_PER_PHYS_BASE+0x1000)
96 #define U300_SYSCON_VBASE		IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
98 #define U300_WDOG_BASE			(U300_SLOW_PER_PHYS_BASE+0x2000)
100 #define U300_UART0_BASE			(U300_SLOW_PER_PHYS_BASE+0x3000)
102 #define U300_TIMER_APP_BASE		(U300_SLOW_PER_PHYS_BASE+0x4000)
103 #define U300_TIMER_APP_VBASE		IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
105 #define U300_KEYPAD_BASE		(U300_SLOW_PER_PHYS_BASE+0x5000)
107 #define U300_GPIO_BASE			(U300_SLOW_PER_PHYS_BASE+0x6000)
109 #define U300_RTC_BASE			(U300_SLOW_PER_PHYS_BASE+0x7000)
111 #define U300_BUSTR_BASE			(U300_SLOW_PER_PHYS_BASE+0x8000)
113 #define U300_EVHIST_BASE		(U300_SLOW_PER_PHYS_BASE+0x9000)
115 #define U300_TIMER_BASE			(U300_SLOW_PER_PHYS_BASE+0xa000)
117 #define U300_PPM_BASE			(U300_SLOW_PER_PHYS_BASE+0xb000)
124 #define U300_ISP_BASE			(0xA0008000)
126 #define U300_DMAC_BASE			(0xC0020000)
128 #define U300_MSL_BASE			(0xc0022000)
130 #define U300_APEX_BASE			(0xc0030000)
132 #define U300_VIDEOENC_BASE		(0xc0080000)
134 #define U300_XGAM_BASE			(0xd0000000)
141 #define U300_SYSCON_CIDR					(0x400)
143 #define U300_SYSCON_SMCR					(0x4d0)
144 #define U300_SYSCON_SMCR_FIELD_MASK				(0x000e)
145 #define U300_SYSCON_SMCR_SEMI_SREFACK_IND			(0x0008)
146 #define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE			(0x0004)
147 #define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE		(0x0002)
149 #define U300_SYSCON_CSDR					(0x4f0)
150 #define U300_SYSCON_CSDR_SW_DEBUG_ENABLE			(0x0001)
152 #define U300_SYSCON_PCR						(0x4f8)
153 #define U300_SYSCON_PCR_SERV_IND				(0x0001)
155 #define U300_SYSCON_BCR						(0x4fc)
156 #define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND		(0x0400)
157 #define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND		(0x0200)
158 #define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK			(0x01FC)
159 #define U300_SYSCON_BCR_APP_BOOT_SERV_MASK			(0x0003)
200 	PIN_CONF_PACKED(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0),
231 		.chipid = 0xb800,
235 		.chipid = 0xc000,
239 		.chipid = 0xc800,
243 		.chipid = 0xd800,
247 		.chipid = 0xe000,
251 		.chipid = 0xe800,
255 		.chipid = 0xf000,
259 		.chipid = 0xf100,
263 		.chipid = 0x0000, /* List terminator */
279 	val = (val & 0xFFU) << 8 | (val >> 8);  in u300_init_check_chip()
284 		if (chip->chipid == (val & 0xFF00U)) {  in u300_init_check_chip()
290 	       "(chip ID 0x%04x)\n", chipname, val);  in u300_init_check_chip()
292 	if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {  in u300_init_check_chip()
340 		"stu300.0", NULL),
358 	syscon_base = of_iomap(syscon, 0);  in u300_init_irq_dt()