arm/mach-tegra/sleep-tegra30.S

1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <asm/asm-offsets.h>
78 	movne	\rd, #(0x3 << 8)		@ 2 devices
143  * Puts the current CPU in wait-for-event mode on the flow controller
144  * and powergates it -- flags (in R0) indicate the request type.
147  * corrupts r0-r4, r10-r12
244 	 * CPU power-gating process, to avoid loading from SDRAM which
245 	 * are not supported once SDRAM is put into self-refresh.
247 	 * disabled before putting SDRAM into self-refresh to avoid
280 	mov	r0, #0                          @ power mode flags (!hotplug)
307  * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
340 	add	r1, r1, #2
376 	 * enabled by the Tegra30 CLK driver on an as-needed basis, see
418 	movweq	r0, #:lower16:TEGRA_EMC_BASE	@ r0 reserved for emc base
449 	orreq	r1, r1, #(1 << 27)	@ set slave mode for channel 1
481 	cmp	r2, #2
484 	/* Issue a ZQ_CAL for dev0 - DDR3 */
485 	mov32	r2, 0x80000011		@ DEV_SELECTION=2, LENGTH=LONG, CMD=1
491 	tst	r1, #2
494 	/* Issue a ZQ_CAL for dev1 - DDR3 */
503 	/* Issue a ZQ_CAL for dev0 - LPDDR2 */
504 	mov32	r2, 0x800A00AB		@ DEV_SELECTION=2, MA=10, OP=0xAB
510 	tst	r1, #2
513 	/* Issue a ZQ_CAL for dev0 - LPDDR2 */
530 	/* Tegra114 had dual EMC channel, now config the other one */
585 	.word	tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
588 	.word	tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
592 	.rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
600  * puts memory in self-refresh for LP0 and LP1
625 	/* 2uS delay delay between changing SCLK and CCLK */
627 	add	r1, r1, #2
639 	/* 2uS delay delay between changing SCLK and disabling PLLs */
641 	add	r1, r1, #2
764 	ldreq	r0, =TEGRA_EMC_BASE	@ r0 reserved for emc base addr
808 	bne	emcself			@ loop until DDR in self-refresh
810 	/* Put VTTGEN in the lowest power mode */
823 	/* Tegra114 had dual EMC channel, now config the other one */
837 	 * and COMP in the lowest power mode when LP1.