arm/mach-tegra/sleep-tegra30.S

1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <asm/asm-offsets.h>
37 #define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
72 #define TEGRA30_POWER_HOTPLUG_SHUTDOWN	(1 << 27) /* Hotplug shutdown */
77 	moveq	\rd, #(0x1 << 8)		@ just 1 device
82 	mov	\rd, #1
92 	tst	\rd, #(1 << 30)
93 	orreq	\rd, \rd, #(1 << 30)
98 	bic	\rd, \rd, #(1 << 18)
102 	orr	\rd, \rd, #(1 << 18)
108 1:
110 	tst	\rd, #(1 << 27)
111 	beq	1b
116 	bic	\rd, \rd, #(1<<\iddq_bit)
122 	orr	\rd, \rd, #(1<<\iddq_bit)
143  * Puts the current CPU in wait-for-event mode on the flow controller
144  * and powergates it -- flags (in R0) indicate the request type.
147  * corrupts r0-r4, r10-r12
173 	moveq	r4, #(1 << 4)			@ wfe bitmap
174 	movne	r4, #(1 << 8)			@ wfi bitmap
183 	subs	r3, r3, #1			@ delay as a part of wfe war.
244 	 * CPU power-gating process, to avoid loading from SDRAM which
245 	 * are not supported once SDRAM is put into self-refresh.
247 	 * disabled before putting SDRAM into self-refresh to avoid
280 	mov	r0, #0                          @ power mode flags (!hotplug)
282 	mov	r0, #1                          @ never return here
307  * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
323 	mov	r1, #(1 << 28)
346 	orr	r1, r1, #(1 << 12)
359 	orr	r1, r1, #(1 << 12)
376 	 * enabled by the Tegra30 CLK driver on an as-needed basis, see
381 	beq	1f
386 	bic	r1, r1, #(1<<31)	@ disable PllP bypass
391 1:
406 	movw	r4, #:lower16:((1 << 28) | (0x4))	@ burst policy is PLLP
407 	movt	r4, #:upper16:((1 << 28) | (0x4))
413 	bic	r1, r1, #(1 << 31)
414 	orr	r1, r1, #(1 << 30)
418 	movweq	r0, #:lower16:TEGRA_EMC_BASE	@ r0 reserved for emc base
437 	orr	r1, r1, #(1 << 30)	@ set DLL_RESET
448 	orr	r1, r1, #(1 << 31)	@ set AUTO_CAL_ACTIVE
449 	orreq	r1, r1, #(1 << 27)	@ set slave mode for channel 1
454 	tst	r1, #(1 << 31)		@ wait until AUTO_CAL_ACTIVE is cleared
458 	bic	r1, r1, #(1 << 31)	@ disable DRAM_CLK_STOP_PD
463 	mov	r1, #1
484 	/* Issue a ZQ_CAL for dev0 - DDR3 */
485 	mov32	r2, 0x80000011		@ DEV_SELECTION=2, LENGTH=LONG, CMD=1
494 	/* Issue a ZQ_CAL for dev1 - DDR3 */
495 	mov32	r2, 0x40000011		@ DEV_SELECTION=1, LENGTH=LONG, CMD=1
503 	/* Issue a ZQ_CAL for dev0 - LPDDR2 */
507 	add	r2, r2, #1
513 	/* Issue a ZQ_CAL for dev0 - LPDDR2 */
514 	mov32	r2, 0x400A00AB		@ DEV_SELECTION=1, MA=10, OP=0xAB
517 	add	r2, r2, #1
530 	/* Tegra114 had dual EMC channel, now config the other one */
585 	.word	tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
588 	.word	tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
592 	.rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
600  * puts memory in self-refresh for LP0 and LP1
623 	mov	r0, #(1 << 28)
646 	bic	r0, r0, #(1 << 12)
653 	orrne	r0, r0, #(1 << 31)	@ enable PllP bypass on fast cluster
654 	bic	r0, r0, #(1 << 30)
656 	beq	1f
659 1:
661 	bic	r0, r0, #(1 << 30)
664 	bic	r0, r0, #(1 << 30)
667 	bic	r0, r0, #(1 << 30)
677 	 * Enable burst on CPU IRQ; bit 24=1
680 	mov	r0, #(1 << 24)
764 	ldreq	r0, =TEGRA_EMC_BASE	@ r0 reserved for emc base addr
776 	bic	r1, r1, #(1 << 28)
777 	bicne	r1, r1, #(1 << 29)
788 	tst	r1, #(1 << 31)		@ wait until AUTO_CAL_ACTIVE is cleared
799 	mov	r1, #1
808 	bne	emcself			@ loop until DDR in self-refresh
810 	/* Put VTTGEN in the lowest power mode */
823 	/* Tegra114 had dual EMC channel, now config the other one */
837 	 * and COMP in the lowest power mode when LP1.