arm/mach-sa1100/pci-nanoengine.c

1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * linux/arch/arm/mach-sa1100/pci-nanoengine.c
7  * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
14 #include <asm/mach-types.h>
22 	if (bus->number != 0 || (devfn >> 3) != 0)  in nanoengine_pci_map_bus()
26 		((bus->number << 16) | (devfn << 8) | (where & ~3));  in nanoengine_pci_map_bus()
45 	.name	= "PCI non-prefetchable",
49 	.end	= NANO_PCI_MEM_RW_PHYS + NANO_PCI_MEM_RW_SIZE - 1,
50 /*	.end	= NANO_PCI_MEM_RW_PHYS + SZ_128K + SZ_8K - 1,*/
55  * nanoEngine PCI reports 1 Megabyte of prefetchable memory, but it
63 pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
64 pci 0000:00:00.0: reg 14: [io  0x0000-0x003f]
65 pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
66 pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
72 pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
73 pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
74 pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff]
75 pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
76 pci 0000:00:00.0: BAR 1: assigned [io  0x0400-0x043f]
77 pci 0000:00:00.0: BAR 1: set to [io  0x0400-0x043f] (PCI address [0x0-0x3f])
79  * On the other hand, if we do not request the prefetchable memory resource,
80  * linux will alloc it first and the two non-prefetchable memory areas that
89 pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
90 pci 0000:00:00.0: reg 14: [io  0x0000-0x003f]
91 pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
92 pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
97 pci 0000:00:00.0: BAR 6: assigned [mem 0x78000000-0x780fffff pref]
98 pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
99 pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
100 pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff]
101 pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
102 pci 0000:00:00.0: BAR 1: assigned [io  0x0400-0x043f]
103 pci 0000:00:00.0: BAR 1: set to [io  0x0400-0x043f] (PCI address [0x0-0x3f])
105 # lspci -vv -s 0000:00:00.0
107 …Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisIN…
108 …Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR+ <PERR+ I…
111         Region 0: Memory at 18620000 (32-bit, non-prefetchable) [size=4K]
113         Region 2: [virtual] Memory at 18600000 (32-bit, non-prefetchable) [size=128K]
116                 Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
117                 Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME-
123 	.name	= "PCI prefetchable",
125 	.end	= 0x78000000 + NANO_PCI_MEM_RW_SIZE - 1,
133 		return -EBUSY;  in pci_nanoengine_setup_resources()
137 		printk(KERN_ERR "PCI: unable to allocate non prefetchable\n");  in pci_nanoengine_setup_resources()
138 		return -EBUSY;  in pci_nanoengine_setup_resources()
143 		printk(KERN_ERR "PCI: unable to allocate prefetchable\n");  in pci_nanoengine_setup_resources()
144 		return -EBUSY;  in pci_nanoengine_setup_resources()
146 	pci_add_resource_offset(&sys->resources, &pci_io_ports, sys->io_offset);  in pci_nanoengine_setup_resources()
147 	pci_add_resource_offset(&sys->resources,  in pci_nanoengine_setup_resources()
148 				&pci_non_prefetchable_memory, sys->mem_offset);  in pci_nanoengine_setup_resources()
149 	pci_add_resource_offset(&sys->resources,  in pci_nanoengine_setup_resources()
150 				&pci_prefetchable_memory, sys->mem_offset);  in pci_nanoengine_setup_resources()
163 		sys->mem_offset = NANO_PCI_MEM_RW_PHYS;  in pci_nanoengine_setup()
164 		sys->io_offset = 0x400;  in pci_nanoengine_setup()