arm/mach-pxa/pxa3xx.c

1 // SPDX-License-Identifier: GPL-2.0-only
3  * linux/arch/arm/mach-pxa/pxa3xx.c
5  * code specific to pxa3xx aka Monahans
9  * 2007-09-02: eric miao <eric.miao@marvell.com>
13 #include <linux/dma/pxa-dma.h>
17 #include <linux/gpio-pxa.h>
25 #include <linux/platform_data/i2c-pxa.h>
31 #include <mach/pxa3xx-regs.h>
33 #include <linux/platform_data/usb-ohci-pxa27x.h>
67  * We disable FIQs across the standby - otherwise, we might receive a
75 		    pm_enter_standby_end - pm_enter_standby_start);  in pxa3xx_cpu_standby()
94  * PXA3xx development kits assumes that the resuming process continues
203 	switch (d->irq) {  in pxa3xx_set_wake()
275 		return -EINVAL;  in pxa3xx_set_wake()
294 	PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);  in pxa_ack_ext_wakeup()
300 	PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);  in pxa_mask_ext_wakeup()
306 	PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);  in pxa_unmask_ext_wakeup()
312 		PWER |= 1 << (d->irq - IRQ_WAKEUP0);  in pxa_set_ext_wakeup_type()
315 		PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);  in pxa_set_ext_wakeup_type()
369 IRQCHIP_DECLARE(pxa3xx_intc, "marvell,pxa-intc", pxa3xx_dt_init_irq);
394  * device registration specific to PXA3xx.
425 	/* PXA25x, PXA27x and PXA3xx common entries */
426 	{ "pxa2xx-ac97", "pcm_pcm_mic_mono", PDMA_FILTER_PARAM(LOWEST, 8) },
427 	{ "pxa2xx-ac97", "pcm_pcm_aux_mono_in", PDMA_FILTER_PARAM(LOWEST, 9) },
428 	{ "pxa2xx-ac97", "pcm_pcm_aux_mono_out",
430 	{ "pxa2xx-ac97", "pcm_pcm_stereo_in", PDMA_FILTER_PARAM(LOWEST, 11) },
431 	{ "pxa2xx-ac97", "pcm_pcm_stereo_out", PDMA_FILTER_PARAM(LOWEST, 12) },
432 	{ "pxa-ssp-dai.0", "rx", PDMA_FILTER_PARAM(LOWEST, 13) },
433 	{ "pxa-ssp-dai.0", "tx", PDMA_FILTER_PARAM(LOWEST, 14) },
434 	{ "pxa-ssp-dai.1", "rx", PDMA_FILTER_PARAM(LOWEST, 15) },
435 	{ "pxa-ssp-dai.1", "tx", PDMA_FILTER_PARAM(LOWEST, 16) },
436 	{ "pxa2xx-ir", "rx", PDMA_FILTER_PARAM(LOWEST, 17) },
437 	{ "pxa2xx-ir", "tx", PDMA_FILTER_PARAM(LOWEST, 18) },
438 	{ "pxa2xx-mci.0", "rx", PDMA_FILTER_PARAM(LOWEST, 21) },
439 	{ "pxa2xx-mci.0", "tx", PDMA_FILTER_PARAM(LOWEST, 22) },
440 	{ "pxa-ssp-dai.2", "rx", PDMA_FILTER_PARAM(LOWEST, 66) },
441 	{ "pxa-ssp-dai.2", "tx", PDMA_FILTER_PARAM(LOWEST, 67) },
443 	/* PXA3xx specific map */
444 	{ "pxa-ssp-dai.3", "rx", PDMA_FILTER_PARAM(LOWEST, 2) },
445 	{ "pxa-ssp-dai.3", "tx", PDMA_FILTER_PARAM(LOWEST, 3) },
446 	{ "pxa2xx-mci.1", "rx", PDMA_FILTER_PARAM(LOWEST, 93) },
447 	{ "pxa2xx-mci.1", "tx", PDMA_FILTER_PARAM(LOWEST, 94) },
448 	{ "pxa3xx-nand", "data", PDMA_FILTER_PARAM(LOWEST, 97) },
449 	{ "pxa2xx-mci.2", "rx", PDMA_FILTER_PARAM(LOWEST, 100) },
450 	{ "pxa2xx-mci.2", "tx", PDMA_FILTER_PARAM(LOWEST, 101) },
471 		 * Note: the last 3 bits DxS are write-1-to-clear so carefully  in pxa3xx_init()