36 #define TS78XX_FPGA_REGS_PHYS_BASE	0xe8000000
37 #define TS78XX_FPGA_REGS_VIRT_BASE	IOMEM(0xff900000)
41 	.id		= 0,
68 	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
81 #define TS_RTC_CTRL	(TS78XX_FPGA_REGS_PHYS_BASE + 0x808)
82 #define TS_RTC_DATA	(TS78XX_FPGA_REGS_PHYS_BASE + 0x80c)
85 	DEFINE_RES_MEM(TS_RTC_CTRL, 0x01),
86 	DEFINE_RES_MEM(TS_RTC_DATA, 0x01),
100 	if (ts78xx_fpga.supports.ts_rtc.init == 0) {  in ts78xx_ts_rtc_load()
122 #define TS_NAND_CTRL	(TS78XX_FPGA_REGS_VIRT_BASE + 0x800)	/* VIRT */
123 #define TS_NAND_DATA	(TS78XX_FPGA_REGS_PHYS_BASE + 0x804)	/* PHYS */
129  * NAND_NCE: bit 0 -> bit 2
131  * NAND_ALE: bit 2 -> bit 0
143 		writeb((readb(TS_NAND_CTRL) & ~0x7) | bits, TS_NAND_CTRL);  in ts78xx_ts_nand_cmd_ctrl()
152 	return readb(TS_NAND_CTRL) & 0x20;  in ts78xx_ts_nand_dev_ready()
210 		.offset		= 0,
268 	if (ts78xx_fpga.supports.ts_nand.init == 0) {  in ts78xx_ts_nand_load()
288 #define TS_RNG_DATA	(TS78XX_FPGA_REGS_PHYS_BASE | 0x044)
311 	if (ts78xx_fpga.supports.ts_rng.init == 0) {  in ts78xx_ts_rng_load()
333 	ts78xx_fpga.supports.ts_rtc.init = 0;  in ts78xx_fpga_devices_zero_init()
334 	ts78xx_fpga.supports.ts_nand.init = 0;  in ts78xx_fpga_devices_zero_init()
335 	ts78xx_fpga.supports.ts_rng.init = 0;  in ts78xx_fpga_devices_zero_init()
357 		switch ((ts78xx_fpga.id >> 8) & 0xffffff) {  in ts78xx_fpga_supports()
359 			pr_warn("unrecognised FPGA revision 0x%.2x\n",  in ts78xx_fpga_supports()
360 				ts78xx_fpga.id & 0xff);  in ts78xx_fpga_supports()
366 			ts78xx_fpga.supports.ts_rtc.present = 0;  in ts78xx_fpga_supports()
367 			ts78xx_fpga.supports.ts_nand.present = 0;  in ts78xx_fpga_supports()
368 			ts78xx_fpga.supports.ts_rng.present = 0;  in ts78xx_fpga_supports()
375 	int tmp, ret = 0;  in ts78xx_fpga_load_devices()
380 			ts78xx_fpga.supports.ts_rtc.present = 0;  in ts78xx_fpga_load_devices()
386 			ts78xx_fpga.supports.ts_nand.present = 0;  in ts78xx_fpga_load_devices()
392 			ts78xx_fpga.supports.ts_rng.present = 0;  in ts78xx_fpga_load_devices()
409 	return 0;  in ts78xx_fpga_unload_devices()
416 	pr_info("FPGA magic=0x%.6x, rev=0x%.2x\n",  in ts78xx_fpga_load()
417 			(ts78xx_fpga.id >> 8) & 0xffffff,  in ts78xx_fpga_load()
418 			ts78xx_fpga.id & 0xff);  in ts78xx_fpga_load()
427 	return 0;  in ts78xx_fpga_load()
445 			"TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n",  in ts78xx_fpga_unload()
446 			(ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff,  in ts78xx_fpga_unload()
447 			(fpga_id >> 8) & 0xffffff, fpga_id & 0xff);  in ts78xx_fpga_unload()
457 	return 0;  in ts78xx_fpga_unload()
463 	if (ts78xx_fpga.state < 0)  in ts78xx_fpga_show()
474 	if (ts78xx_fpga.state < 0) {  in ts78xx_fpga_store()
479 	if (strncmp(buf, "online", sizeof("online") - 1) == 0)  in ts78xx_fpga_store()
481 	else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0)  in ts78xx_fpga_store()
482 		value = 0;  in ts78xx_fpga_store()
489 	ret = (ts78xx_fpga.state == 0)  in ts78xx_fpga_store()
493 	if (!(ret < 0))  in ts78xx_fpga_store()
528 	 * MPP[21] PCI Clock Out 0
534 	0,
569 	.atag_offset	= 0x100,