Lines Matching +full:try +full:- +full:power +full:- +full:role
1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
5 * Copyright (C) 2009-2011 Nokia Corporation
12 * XXX these should be marked initdata for multi-OMAP kernels
15 #include <linux/platform_data/i2c-omap.h>
16 #include <linux/power/smartreflex.h>
17 #include <linux/platform_data/hsmmc-omap.h>
25 #include "prm-regbits-34xx.h"
26 #include "cm-regbits-34xx.h"
37 * is driver-specific or driver-kernel integration-specific belongs
287 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
335 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
410 * UART4 is extremely unclear and opaque; it is unclear what the role
416 { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
447 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
448 { .role = "tv_clk", .clk = "dss_tv_fck" },
450 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
542 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
560 { .role = "ick", .clk = "dss_ick" },
579 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
664 { .role = "dbclk", .clk = "gpio1_dbck", },
685 { .role = "dbclk", .clk = "gpio2_dbck", },
706 { .role = "dbclk", .clk = "gpio3_dbck", },
727 { .role = "dbclk", .clk = "gpio4_dbck", },
749 { .role = "dbclk", .clk = "gpio5_dbck", },
771 { .role = "dbclk", .clk = "gpio6_dbck", },
796 .rev_offs = -ENODEV,
811 { .role = "pad_fck", .clk = "mcbsp_clks" },
812 { .role = "prcm_fck", .clk = "core_96m_fck" },
816 { .role = "pad_fck", .clk = "mcbsp_clks" },
817 { .role = "prcm_fck", .clk = "per_96m_fck" },
902 .rev_offs = -ENODEV,
931 .rev_offs = -ENODEV,
943 .rev_offs = -ENODEV,
1028 * mailbox module allowing communication between the on-chip processors
1029 * using a queued mailbox-interrupt mechanism.
1175 * Enabling the device in any other MIDLEMODE setting but force-idle
1178 * signal when MIDLEMODE is set to force-idle.
1219 { .role = "dbck", .clk = "omap_32k_fck", },
1269 { .role = "dbck", .clk = "omap_32k_fck", },
1313 { .role = "dbck", .clk = "omap_32k_fck", },
1333 * high-speed multi-port usb host controller
1369 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1374 * - USBHOST module is set to smart-idle mode
1375 * - PRCM asserts idle_req to the USBHOST module ( This typically
1376 * happens when the system is going to a low power mode : all ports
1379 * - an USBHOST interrupt occurs before the module is able to answer
1389 * Errata: USB host EHCI may stall when entering smart-standby mode
1393 * When the USBHOST module is set to smart-standby mode, and when it is
1515 /* L3 -> L4_CORE interface */
1522 /* L3 -> L4_PER interface */
1530 /* MPU -> L3 interface */
1538 /* l3 -> debugss */
1545 /* DSS -> l3 */
1564 /* l3_core -> usbhsotg interface */
1572 /* l3_core -> am35xx_usbhsotg interface */
1580 /* l3_core -> sad2d interface */
1588 /* L4_CORE -> L4_WKUP interface */
1595 /* L4 CORE -> MMC1 interface */
1612 /* L4 CORE -> MMC2 interface */
1629 /* L4 CORE -> MMC3 interface */
1639 /* L4 CORE -> UART1 interface */
1648 /* L4 CORE -> UART2 interface */
1657 /* L4 PER -> UART3 interface */
1666 /* L4 PER -> UART4 interface */
1675 /* AM35xx: L4 CORE -> UART4 interface */
1684 /* L4 CORE -> I2C1 interface */
1699 /* L4 CORE -> I2C2 interface */
1714 /* L4 CORE -> I2C3 interface */
1730 /* L4 CORE -> SR1 interface */
1745 /* L4 CORE -> SR2 interface */
1762 /* l4_core -> usbhsotg */
1771 /* l4_core -> usbhsotg */
1779 /* L4_WKUP -> L4_SEC interface */
1786 /* IVA2 <- L3 interface */
1794 /* l4_per -> timer3 */
1803 /* l4_per -> timer4 */
1812 /* l4_per -> timer5 */
1821 /* l4_per -> timer6 */
1830 /* l4_per -> timer7 */
1839 /* l4_per -> timer8 */
1848 /* l4_per -> timer9 */
1856 /* l4_core -> timer10 */
1864 /* l4_core -> timer11 */
1872 /* l4_wkup -> wd_timer2 */
1881 /* l4_core -> dss */
1910 /* l4_core -> dss_dispc */
1925 /* l4_core -> dss_dsi1 */
1940 /* l4_core -> dss_rfbi */
1955 /* l4_core -> dss_venc */
1971 /* l4_wkup -> gpio1 */
1979 /* l4_per -> gpio2 */
1987 /* l4_per -> gpio3 */
2019 /* l4_core -> mmu isp */
2041 /* l3_main -> iva mmu */
2065 /* l4_per -> gpio4 */
2073 /* l4_per -> gpio5 */
2081 /* l4_per -> gpio6 */
2089 /* l4_core -> mcbsp1 */
2098 /* l4_per -> mcbsp2 */
2107 /* l4_per -> mcbsp3 */
2116 /* l4_per -> mcbsp4 */
2125 /* l4_core -> mcbsp5 */
2134 /* l4_per -> mcbsp2_sidetone */
2143 /* l4_per -> mcbsp3_sidetone */
2151 /* l4_core -> mailbox */
2158 /* l4 core -> mcspi1 interface */
2166 /* l4 core -> mcspi2 interface */
2174 /* l4 core -> mcspi3 interface */
2182 /* l4 core -> mcspi4 interface */
2214 /* l4_core -> hdq1w interface */
2237 * so is left as a future to-do item.
2246 /* l4_core -> davinci mdio */
2250 * so is left as a future to-do item.
2269 * http://www.spinics.net/lists/arm-kernel/msg174734.html
2274 /* l3_core -> davinci emac interface */
2278 * so is left as a future to-do item.
2287 /* l4_core -> davinci emac */
2291 * so is left as a future to-do item.
2307 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
2347 * synchronous serial interface (multichannel and full-duplex serial if)
2379 /* L4 CORE -> SSI */
2448 * http://www.spinics.net/lists/arm-kernel/msg215466.html So
2449 * if you need these IP blocks on an AM35xx, try uncommenting
2457 /* 3430ES1-only hwmod links */
2464 /* 3430ES2+-only hwmod links */
2476 /* <= 3430ES3-only hwmod links */
2483 /* 3430ES3+-only hwmod links */
2490 /* 34xx-only hwmod links (all ES revisions) */
2504 /* 36xx-only hwmod links (all ES revisions) */
2556 * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible?
2557 * @bus: struct device_node * for the top-level OMAP DT data
2564 * fused as a 'general-purpose' SoC. If however DT data is present,
2623 return -EINVAL; in omap3xxx_hwmod_init()
2686 * long-term fix to this is to ensure hwmods are set up in in omap3xxx_hwmod_init()