Lines Matching +full:emc +full:- +full:mode +full:- +full:4

2  * arch/arm/mach-lpc32xx/suspend.S
41 	stmfd	r0!, {r3 - r7, sp, lr}
46 	ldr	EMCBASE_REG, [WORK1_REG, #4]
65 	@ Setup self-refresh with support for manual exit of
66 	@ self-refresh mode
72 	@ Wait for self-refresh acknowledge, clocks to the DRAM device
73 	@ will automatically stop on start of self-refresh
78 	bne	3b @ Branch until self-refresh mode starts
80 	@ Enter direct-run mode from run mode
84 	@ Safe disable of DRAM clock in EMC block, prevents DDR sync
97 	@ Enter stop mode until an enabled event occurs
110 4:
113 	bne	4b
115 	@ Re-enter run mode with self-refresh flag cleared, but no DRAM
116 	@ update yet. DRAM is still in self-refresh
120 	@ Restore original DRAM clock mode to restore DRAM clocks
124 	@ Clear self-refresh mode
131 	@ Wait for EMC to clear self-refresh mode
135 	bne	5b @ Branch until self-refresh has exited
139 	ldmfd	r0!, {r3 - r7, sp, pc}
150 	.word	. - lpc32xx_sys_suspend