1 // SPDX-License-Identifier: GPL-2.0-or-later
59 #define to_mmdc_pmu(p) container_of(p, struct mmdc_pmu, pmu)
75 	{ .compatible = "fsl,imx6q-mmdc", .data = (void *)&imx6q_data},
76 	{ .compatible = "fsl,imx6qp-mmdc", .data = (void *)&imx6qp_data},
85 PMU_EVENT_ATTR_STRING(total-cycles, mmdc_pmu_total_cycles, "event=0x00")
86 PMU_EVENT_ATTR_STRING(busy-cycles, mmdc_pmu_busy_cycles, "event=0x01")
87 PMU_EVENT_ATTR_STRING(read-accesses, mmdc_pmu_read_accesses, "event=0x02")
88 PMU_EVENT_ATTR_STRING(write-accesses, mmdc_pmu_write_accesses, "event=0x03")
89 PMU_EVENT_ATTR_STRING(read-bytes, mmdc_pmu_read_bytes, "event=0x04")
90 PMU_EVENT_ATTR_STRING(read-bytes.unit, mmdc_pmu_read_bytes_unit, "MB");
91 PMU_EVENT_ATTR_STRING(read-bytes.scale, mmdc_pmu_read_bytes_scale, "0.000001");
92 PMU_EVENT_ATTR_STRING(write-bytes, mmdc_pmu_write_bytes, "event=0x05")
93 PMU_EVENT_ATTR_STRING(write-bytes.unit, mmdc_pmu_write_bytes_unit, "MB");
94 PMU_EVENT_ATTR_STRING(write-bytes.scale, mmdc_pmu_write_bytes_scale, "0.000001");
97 	struct pmu pmu;  member
109  * Polling period is set to one second, overflow of total-cycles (the fastest
127 	return cpumap_print_to_pagebuf(true, buf, &pmu_mmdc->cpu);  in mmdc_pmu_cpumask_show()
161 PMU_FORMAT_ATTR(event, "config:0-63");
162 PMU_FORMAT_ATTR(axi_id, "config1:0-63");
186 	mmdc_base = pmu_mmdc->mmdc_base;  in mmdc_pmu_read_counter()
219 	if (!cpumask_test_and_clear_cpu(cpu, &pmu_mmdc->cpu))  in mmdc_pmu_offline_cpu()
226 	perf_pmu_migrate_context(&pmu_mmdc->pmu, cpu, target);  in mmdc_pmu_offline_cpu()
227 	cpumask_set_cpu(target, &pmu_mmdc->cpu);  in mmdc_pmu_offline_cpu()
233 					  struct pmu *pmu,  in mmdc_pmu_group_event_is_valid()  argument
236 	int cfg = event->attr.config;  in mmdc_pmu_group_event_is_valid()
241 	if (event->pmu != pmu)  in mmdc_pmu_group_event_is_valid()
248  * Each event has a single fixed-purpose counter, so we can only have a
255 	struct pmu *pmu = event->pmu;  in mmdc_pmu_group_is_valid()  local
256 	struct perf_event *leader = event->group_leader;  in mmdc_pmu_group_is_valid()
260 	set_bit(leader->attr.config, &counter_mask);  in mmdc_pmu_group_is_valid()
263 		if (!mmdc_pmu_group_event_is_valid(event, pmu, &counter_mask))  in mmdc_pmu_group_is_valid()
268 		if (!mmdc_pmu_group_event_is_valid(sibling, pmu, &counter_mask))  in mmdc_pmu_group_is_valid()
277 	struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);  in mmdc_pmu_event_init()
278 	int cfg = event->attr.config;  in mmdc_pmu_event_init()
280 	if (event->attr.type != event->pmu->type)  in mmdc_pmu_event_init()
281 		return -ENOENT;  in mmdc_pmu_event_init()
283 	if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)  in mmdc_pmu_event_init()
284 		return -EOPNOTSUPP;  in mmdc_pmu_event_init()
286 	if (event->cpu < 0) {  in mmdc_pmu_event_init()
287 		dev_warn(pmu_mmdc->dev, "Can't provide per-task data!\n");  in mmdc_pmu_event_init()
288 		return -EOPNOTSUPP;  in mmdc_pmu_event_init()
291 	if (event->attr.sample_period)  in mmdc_pmu_event_init()
292 		return -EINVAL;  in mmdc_pmu_event_init()
295 		return -EINVAL;  in mmdc_pmu_event_init()
298 		return -EINVAL;  in mmdc_pmu_event_init()
300 	event->cpu = cpumask_first(&pmu_mmdc->cpu);  in mmdc_pmu_event_init()
306 	struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);  in mmdc_pmu_event_update()
307 	struct hw_perf_event *hwc = &event->hw;  in mmdc_pmu_event_update()
311 		prev_raw_count = local64_read(&hwc->prev_count);  in mmdc_pmu_event_update()
313 						      event->attr.config);  in mmdc_pmu_event_update()
314 	} while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,  in mmdc_pmu_event_update()
317 	delta = (new_raw_count - prev_raw_count) & 0xFFFFFFFF;  in mmdc_pmu_event_update()
319 	local64_add(delta, &event->count);  in mmdc_pmu_event_update()
324 	struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);  in mmdc_pmu_event_start()
325 	struct hw_perf_event *hwc = &event->hw;  in mmdc_pmu_event_start()
329 	mmdc_base = pmu_mmdc->mmdc_base;  in mmdc_pmu_event_start()
336 	hrtimer_start(&pmu_mmdc->hrtimer, mmdc_pmu_timer_period(),  in mmdc_pmu_event_start()
339 	local64_set(&hwc->prev_count, 0);  in mmdc_pmu_event_start()
346 	val = event->attr.config1;  in mmdc_pmu_event_start()
352 	if (pmu_mmdc->devtype_data->flags & MMDC_FLAG_PROFILE_SEL)  in mmdc_pmu_event_start()
360 	struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);  in mmdc_pmu_event_add()
361 	struct hw_perf_event *hwc = &event->hw;  in mmdc_pmu_event_add()
363 	int cfg = event->attr.config;  in mmdc_pmu_event_add()
368 	if (pmu_mmdc->mmdc_events[cfg] != NULL)  in mmdc_pmu_event_add()
369 		return -EAGAIN;  in mmdc_pmu_event_add()
371 	pmu_mmdc->mmdc_events[cfg] = event;  in mmdc_pmu_event_add()
372 	pmu_mmdc->active_events++;  in mmdc_pmu_event_add()
374 	local64_set(&hwc->prev_count, mmdc_pmu_read_counter(pmu_mmdc, cfg));  in mmdc_pmu_event_add()
381 	struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);  in mmdc_pmu_event_stop()
384 	mmdc_base = pmu_mmdc->mmdc_base;  in mmdc_pmu_event_stop()
397 	struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);  in mmdc_pmu_event_del()
398 	int cfg = event->attr.config;  in mmdc_pmu_event_del()
400 	pmu_mmdc->mmdc_events[cfg] = NULL;  in mmdc_pmu_event_del()
401 	pmu_mmdc->active_events--;  in mmdc_pmu_event_del()
403 	if (pmu_mmdc->active_events == 0)  in mmdc_pmu_event_del()
404 		hrtimer_cancel(&pmu_mmdc->hrtimer);  in mmdc_pmu_event_del()
414 		struct perf_event *event = pmu_mmdc->mmdc_events[i];  in mmdc_pmu_overflow_handler()
438 		.pmu = (struct pmu) {  in mmdc_pmu_init()
463 	cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node);  in imx_mmdc_remove()
464 	perf_pmu_unregister(&pmu_mmdc->pmu);  in imx_mmdc_remove()
476 		of_match_device(imx_mmdc_dt_ids, &pdev->dev);  in imx_mmdc_perf_init()
480 		pr_err("failed to allocate PMU device!\n");  in imx_mmdc_perf_init()
481 		return -ENOMEM;  in imx_mmdc_perf_init()
496 	mmdc_num = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev);  in imx_mmdc_perf_init()
500 		name = devm_kasprintf(&pdev->dev,  in imx_mmdc_perf_init()
503 	pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data;  in imx_mmdc_perf_init()
505 	hrtimer_init(&pmu_mmdc->hrtimer, CLOCK_MONOTONIC,  in imx_mmdc_perf_init()
507 	pmu_mmdc->hrtimer.function = mmdc_pmu_timer_handler;  in imx_mmdc_perf_init()
509 	cpumask_set_cpu(raw_smp_processor_id(), &pmu_mmdc->cpu);  in imx_mmdc_perf_init()
511 	/* Register the pmu instance for cpu hotplug */  in imx_mmdc_perf_init()
512 	cpuhp_state_add_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node);  in imx_mmdc_perf_init()
514 	ret = perf_pmu_register(&(pmu_mmdc->pmu), name, -1);  in imx_mmdc_perf_init()
522 	pr_warn("MMDC Perf PMU failed (%d), disabled\n", ret);  in imx_mmdc_perf_init()
523 	cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node);  in imx_mmdc_perf_init()
524 	hrtimer_cancel(&pmu_mmdc->hrtimer);  in imx_mmdc_perf_init()
537 	struct device_node *np = pdev->dev.of_node;  in imx_mmdc_probe()
544 	mmdc_ipg_clk = devm_clk_get(&pdev->dev, NULL);  in imx_mmdc_probe()
550 		dev_err(&pdev->dev, "Unable to enable mmdc ipg clock.\n");  in imx_mmdc_probe()
558 	/* Get ddr type */  in imx_mmdc_probe()
580 		.name	= "imx-mmdc",