Lines Matching +full:0 +full:xf0000000
19 * the synchronous boot mode is selected. When ASDO is "0" (i.e
23 * 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous
24 * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
25 * decoded at 0xf0000000.
34 #define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */
35 #define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */
36 #define EP93XX_CS1_PHYS_BASE 0x10000000
37 #define EP93XX_CS2_PHYS_BASE 0x20000000
38 #define EP93XX_CS3_PHYS_BASE 0x30000000
39 #define EP93XX_PCMCIA_PHYS_BASE 0x40000000
40 #define EP93XX_CS6_PHYS_BASE 0x60000000
41 #define EP93XX_CS7_PHYS_BASE 0x70000000
42 #define EP93XX_SDCE0_PHYS_BASE 0xc0000000
43 #define EP93XX_SDCE1_PHYS_BASE 0xd0000000
44 #define EP93XX_SDCE2_PHYS_BASE 0xe0000000
45 #define EP93XX_SDCE3_PHYS_BASE_ASYNC 0xf0000000 /* ASDO Pin = 0 */
46 #define EP93XX_CS0_PHYS_BASE_SYNC 0xf0000000 /* ASDO Pin = 1 */
49 #define EP93XX_DMA_BASE EP93XX_AHB_IOMEM(0x00000000)
51 #define EP93XX_ETHERNET_PHYS_BASE EP93XX_AHB_PHYS(0x00010000)
52 #define EP93XX_ETHERNET_BASE EP93XX_AHB_IOMEM(0x00010000)
54 #define EP93XX_USB_PHYS_BASE EP93XX_AHB_PHYS(0x00020000)
55 #define EP93XX_USB_BASE EP93XX_AHB_IOMEM(0x00020000)
57 #define EP93XX_RASTER_PHYS_BASE EP93XX_AHB_PHYS(0x00030000)
58 #define EP93XX_RASTER_BASE EP93XX_AHB_IOMEM(0x00030000)
60 #define EP93XX_GRAPHICS_ACCEL_BASE EP93XX_AHB_IOMEM(0x00040000)
62 #define EP93XX_SDRAM_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00060000)
64 #define EP93XX_PCMCIA_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00080000)
66 #define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000)
68 #define EP93XX_IDE_PHYS_BASE EP93XX_AHB_PHYS(0x000a0000)
69 #define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000)
71 #define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000)
73 #define EP93XX_VIC2_BASE EP93XX_AHB_IOMEM(0x000c0000)
76 #define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000)
78 #define EP93XX_I2S_PHYS_BASE EP93XX_APB_PHYS(0x00020000)
79 #define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000)
81 #define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000)
83 #define EP93XX_AAC_PHYS_BASE EP93XX_APB_PHYS(0x00080000)
84 #define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000)
86 #define EP93XX_SPI_PHYS_BASE EP93XX_APB_PHYS(0x000a0000)
87 #define EP93XX_SPI_BASE EP93XX_APB_IOMEM(0x000a0000)
89 #define EP93XX_IRDA_BASE EP93XX_APB_IOMEM(0x000b0000)
91 #define EP93XX_KEY_MATRIX_PHYS_BASE EP93XX_APB_PHYS(0x000f0000)
92 #define EP93XX_KEY_MATRIX_BASE EP93XX_APB_IOMEM(0x000f0000)
94 #define EP93XX_ADC_PHYS_BASE EP93XX_APB_PHYS(0x00100000)
95 #define EP93XX_ADC_BASE EP93XX_APB_IOMEM(0x00100000)
96 #define EP93XX_TOUCHSCREEN_BASE EP93XX_APB_IOMEM(0x00100000)
98 #define EP93XX_PWM_PHYS_BASE EP93XX_APB_PHYS(0x00110000)
99 #define EP93XX_PWM_BASE EP93XX_APB_IOMEM(0x00110000)
101 #define EP93XX_RTC_PHYS_BASE EP93XX_APB_PHYS(0x00120000)
102 #define EP93XX_RTC_BASE EP93XX_APB_IOMEM(0x00120000)
104 #define EP93XX_WATCHDOG_PHYS_BASE EP93XX_APB_PHYS(0x00140000)
105 #define EP93XX_WATCHDOG_BASE EP93XX_APB_IOMEM(0x00140000)
108 #define EP93XX_SYSCON_BASE EP93XX_APB_IOMEM(0x00130000)
110 #define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
111 #define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
127 #define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
128 #define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
129 #define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20)
131 #define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24)
134 #define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80)
164 #define EP93XX_SYSCON_DEVCFG_SHENA (1<<0)
165 #define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84)
170 #define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c)
175 #define EP93XX_I2SCLKDIV_LRDIV32 (0 << 17)
179 #define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90)
183 #define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
184 #define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c)
185 #define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000)
194 #define EP93XX_SYSCON_SYSCFG_LCSN1 (1<<0)
195 #define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
203 ep93xx_devcfg_set_clear(bits, 0x00); in ep93xx_devcfg_set_bits()
208 ep93xx_devcfg_set_clear(0x00, bits); in ep93xx_devcfg_clear_bits()