arm/kernel/entry-header.S

1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/asm-offsets.h>
9 #include <asm/uaccess-asm.h>
13 @ -----------------
30  * (due to slow/fast restore user regs).
60  * ARMv7-M exception entry/exit macros.
66  * If exception is taken while in user mode, SP_main is
75  * When returning to kernel mode, we don't return from exception.
79 	@ exception entry. Depending on the mode the cpu was in when the
87 	@ we cannot rely on r0-r3 and r12 matching the value saved in the
88 	@ exception frame because of tail-chaining. So these have to be
90 	ldmia	r12!, {r0-r3}
95 	sub	sp, #PT_REGS_SIZE-S_IP
96 	stmdb	sp!, {r0-r11}
99 	@ r0-r7 are used for signals and never touched from now on. Clobbering
100 	@ r8-r12 is OK.
102 	ldmia	r9!, {r8, r10-r12}
107 	@ The cpu might automatically 8-byte align the stack. Bit 9
109 	@ another 32-bit value is included in the stack.
117 	@ store r13-r15, xPSR
118 	stmia	r8!, {r9-r12}
136 	ldmia	r12, {r1-r5}
138 	@ an exception frame is always 8-byte aligned. To tell the hardware if
151 	stmdb	r2!, {r1, r3-r5}
152 	ldmia	sp, {r1, r3-r5}
154 	stmdb	r2!, {r0, r3-r5}
156 	stmdb	r2!, {r1, r3-r5}
162 	@ restore original r4-r11
163 	ldmia	sp!, {r0-r11}
166 	add	sp, sp, #PT_REGS_SIZE-S_IP
175 	@ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not
176 	@ available. Should only be called from SVC mode
181 	msr	cpsr_c, \rtemp			@ switch to the SYS mode
187 	msr	cpsr_c, \rtemp			@ switch back to the SVC mode
193 	msr	cpsr_c, \rtemp			@ switch to the SYS mode
199 	msr	cpsr_c, \rtemp			@ switch back to the SVC mode
224 	@ ARM mode SVC restore
227 	@ We must avoid clrex due to Cortex-A15 erratum #830321
231 	ldmia	sp, {r0 - pc}^			@ load r0 - pc, cpsr
233 	@ Thumb mode SVC restore
237 	@ We must avoid clrex due to Cortex-A15 erratum #830321
241 	ldmia	sp, {r0 - r12}
249 	@ svc_exit_via_fiq - like svc_exit but switches to FIQ mode before exit
252 	@ mode to restore the final part of the register state.
260 	@ supplied rpsr. This is because the FIQ exceptions are not re-entrant
267 	@ ARM mode restore
269 	ldmib	r0, {r1 - r14}	@ abort is deadly from here onward (it will
278 	@ Thumb mode restore
283 	ldmia	r0, {r2 - r12}
288 	ldmia	r0, {r0 - r1}
294 	.macro	restore_user_regs, fast = 0, offset = 0  argument
297 	@ ARM mode restore
305 	@ We must avoid clrex due to Cortex-A15 erratum #830321
308 	.if	\fast
309 	ldmdb	r2, {r1 - lr}^			@ get calling r1 - lr
311 	ldmdb	r2, {r0 - lr}^			@ get calling r0 - lr
325 	v7m_exception_slow_exit ret_r0 = \fast
327 	@ Thumb mode restore
337 	@ We must avoid clrex due to Cortex-A15 erratum #830321
340 	.if	\fast
341 	ldmdb	sp, {r1 - r12}			@ get calling r1 - r12
343 	ldmdb	sp, {r0 - r12}			@ get calling r0 - r12
345 	add	sp, sp, #PT_REGS_SIZE - S_SP
353  * between user and kernel mode.
358 	stmdb   sp!, {r0-r3, ip, lr}
360 	ldmia	sp!, {r0-r3, ip, lr}
370 	stmdb   sp!, {r0-r3, ip, lr}
372 	ldmia	sp!, {r0-r3, ip, lr}
388 	ldmiacc	r1, {r0 - r6}			@ reload r0-r6
397 	ldmiacc	r1, {r0 - r6}			@ reload r0-r6
406  * have in theory up to 7 arguments to a function - r0 to r6.
408  * r7 is reserved for the system call number for thumb mode.