arm/crypto/sha512-core.S_shipped

1 @ SPDX-License-Identifier: GPL-2.0
21 @ by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue
26 @ Rescheduling for dual-issue pipeline resulted in 6% improvement on
31 @ Profiler-assisted and platform-specific optimization resulted in 7%
37 @ one byte in 23.3 cycles or ~60% faster than integer-only code.
43 @ Technical writers asserted that 3-way S4 pipeline can sustain
45 @ not be observed, see https://www.openssl.org/~appro/Snapdragon-S4.html
46 @ for further details. On side note Cortex-A15 processes one byte in
52 @ h[0-7], namely with most significant dword at *lower* address, which
54 @ expected to maintain native byte order for whole 64-bit values.
57 # define VFP_ABI_PUSH	vstmdb	sp!,{d8-d15}
58 # define VFP_ABI_POP	vldmia	sp!,{d8-d15}
131 .size	K512,.-K512
134 .word	OPENSSL_armcap_P-sha512_block_data_order
135 .skip	32-4
156 	stmdb	sp!,{r4-r12,lr}
214 	@ Sigma1(x)	(ROTR((x),14) ^ ROTR((x),18)  ^ ROTR((x),41))
215 	@ LO		lo>>14^hi<<18 ^ lo>>18^hi<<14 ^ hi>>9^lo<<23
216 	@ HI		hi>>14^lo<<18 ^ hi>>18^lo<<14 ^ lo>>9^hi<<23
221 	eor	r9,r9,r8,lsl#18
223 	eor	r10,r10,r7,lsl#18
225 	eor	r9,r9,r7,lsr#18
226 	eor	r10,r10,r8,lsr#18
273 	@ LO		lo>>28^hi<<4  ^ hi>>2^lo<<30 ^ hi>>7^lo<<25
274 	@ HI		hi>>28^lo<<4  ^ lo>>2^hi<<30 ^ lo>>7^hi<<25
285 	eor	r9,r9,r5,lsl#25
286 	eor	r10,r10,r6,lsl#25	@ Sigma0(a)
312 	@ LO		lo>>1^hi<<31  ^ lo>>8^hi<<24 ^ lo>>7^hi<<25
326 	eor	r3,r3,r10,lsl#25
354 	@ Sigma1(x)	(ROTR((x),14) ^ ROTR((x),18)  ^ ROTR((x),41))
355 	@ LO		lo>>14^hi<<18 ^ lo>>18^hi<<14 ^ hi>>9^lo<<23
356 	@ HI		hi>>14^lo<<18 ^ hi>>18^lo<<14 ^ lo>>9^hi<<23
361 	eor	r9,r9,r8,lsl#18
363 	eor	r10,r10,r7,lsl#18
365 	eor	r9,r9,r7,lsr#18
366 	eor	r10,r10,r8,lsr#18
413 	@ LO		lo>>28^hi<<4  ^ hi>>2^lo<<30 ^ hi>>7^lo<<25
414 	@ HI		hi>>28^lo<<4  ^ lo>>2^hi<<30 ^ lo>>7^hi<<25
425 	eor	r9,r9,r5,lsl#25
426 	eor	r10,r10,r6,lsl#25	@ Sigma0(a)
525 	ldmia	sp!,{r4-r12,pc}
527 	ldmia	sp!,{r4-r12,lr}
530 	.word	0xe12fff1e			@ interoperable with Thumb ISA:-)
532 .size	sha512_block_data_order,.-sha512_block_data_order
534 .arch	armv7-a
546 	sub	r3,r3,.Lsha512_block_data_order-K512
547 	vldmia	r0,{d16-d23}		@ load context
553 	vshr.u64	d25,d20,#18
578 	vsli.64		d26,d16,#25
590 	vshr.u64	d25,d19,#18
615 	vsli.64		d26,d23,#25
627 	vshr.u64	d25,d18,#18
652 	vsli.64		d26,d22,#25
664 	vshr.u64	d25,d17,#18
689 	vsli.64		d26,d21,#25
701 	vshr.u64	d25,d16,#18
726 	vsli.64		d26,d20,#25
738 	vshr.u64	d25,d23,#18
763 	vsli.64		d26,d19,#25
775 	vshr.u64	d25,d22,#18
800 	vsli.64		d26,d18,#25
812 	vshr.u64	d25,d21,#18
837 	vsli.64		d26,d17,#25
849 	vshr.u64	d25,d20,#18
874 	vsli.64		d26,d16,#25
886 	vshr.u64	d25,d19,#18
911 	vsli.64		d26,d23,#25
923 	vshr.u64	d25,d18,#18
948 	vsli.64		d26,d22,#25
960 	vshr.u64	d25,d17,#18
985 	vsli.64		d26,d21,#25
997 	vshr.u64	d25,d16,#18
1022 	vsli.64		d26,d20,#25
1034 	vshr.u64	d25,d23,#18
1059 	vsli.64		d26,d19,#25
1071 	vshr.u64	d25,d22,#18
1096 	vsli.64		d26,d18,#25
1108 	vshr.u64	d25,d21,#18
1133 	vsli.64		d26,d17,#25
1163 	vshr.u64	d25,d20,#18		@ from NEON_00_15
1187 	vsli.64		d26,d16,#25
1199 	vshr.u64	d25,d19,#18
1224 	vsli.64		d26,d23,#25
1251 	vshr.u64	d25,d18,#18		@ from NEON_00_15
1260 #if 18<16 && defined(__ARMEL__)
1275 	vsli.64		d26,d22,#25
1287 	vshr.u64	d25,d17,#18
1312 	vsli.64		d26,d21,#25
1339 	vshr.u64	d25,d16,#18		@ from NEON_00_15
1363 	vsli.64		d26,d20,#25
1375 	vshr.u64	d25,d23,#18
1400 	vsli.64		d26,d19,#25
1427 	vshr.u64	d25,d22,#18		@ from NEON_00_15
1451 	vsli.64		d26,d18,#25
1463 	vshr.u64	d25,d21,#18
1488 	vsli.64		d26,d17,#25
1515 	vshr.u64	d25,d20,#18		@ from NEON_00_15
1539 	vsli.64		d26,d16,#25
1547 	vshr.u64	d24,d19,#14	@ 25
1548 #if 25<16
1551 	vshr.u64	d25,d19,#18
1552 #if 25>0
1561 #if 25<16 && defined(__ARMEL__)
1576 	vsli.64		d26,d23,#25
1603 	vshr.u64	d25,d18,#18		@ from NEON_00_15
1627 	vsli.64		d26,d22,#25
1639 	vshr.u64	d25,d17,#18
1664 	vsli.64		d26,d21,#25
1691 	vshr.u64	d25,d16,#18		@ from NEON_00_15
1715 	vsli.64		d26,d20,#25
1727 	vshr.u64	d25,d23,#18
1752 	vsli.64		d26,d19,#25
1779 	vshr.u64	d25,d22,#18		@ from NEON_00_15
1803 	vsli.64		d26,d18,#25
1815 	vshr.u64	d25,d21,#18
1840 	vsli.64		d26,d17,#25
1851 	vldmia		r0,{d24-d31}	@ load context to temp
1856 	vstmia		r0,{d16-d23}	@ save context
1863 .size	sha512_block_data_order_neon,.-sha512_block_data_order_neon