Lines Matching +full:gic +full:- +full:timer
1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A9 MPCore (V2P-CA9)
8 * HBI-0191B
11 /dts-v1/;
12 #include "vexpress-v2m.dtsi"
15 model = "V2P-CA9";
18 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
35 #address-cells = <1>;
36 #size-cells = <0>;
40 compatible = "arm,cortex-a9";
42 next-level-cache = <&L2>;
47 compatible = "arm,cortex-a9";
49 next-level-cache = <&L2>;
54 compatible = "arm,cortex-a9";
56 next-level-cache = <&L2>;
61 compatible = "arm,cortex-a9";
63 next-level-cache = <&L2>;
72 reserved-memory {
73 #address-cells = <1>;
74 #size-cells = <1>;
80 compatible = "shared-dma-pool";
82 no-map;
89 interrupt-names = "combined";
92 clock-names = "clcdclk", "apb_pclk";
94 max-memory-bandwidth = <95000000>;
98 remote-endpoint = <&dvi_bridge_in_ct>;
99 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
104 memory-controller@100e0000 {
108 clock-names = "apb_pclk";
111 memory-controller@100e1000 {
117 clock-names = "apb_pclk";
120 timer@100e4000 {
126 clock-names = "timer0clk", "timer1clk", "apb_pclk";
135 clock-names = "wdog_clk", "apb_pclk";
139 compatible = "arm,cortex-a9-scu";
143 timer@1e000600 {
144 compatible = "arm,cortex-a9-twd-timer";
150 compatible = "arm,cortex-a9-twd-wdt";
155 gic: interrupt-controller@1e001000 { label
156 compatible = "arm,cortex-a9-gic";
157 #interrupt-cells = <3>;
158 #address-cells = <0>;
159 interrupt-controller;
164 L2: cache-controller@1e00a000 {
165 compatible = "arm,pl310-cache";
168 cache-unified;
169 cache-level = <2>;
170 arm,data-latency = <1 1 1>;
171 arm,tag-latency = <1 1 1>;
175 compatible = "arm,cortex-a9-pmu";
180 interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;
185 compatible = "arm,vexpress,config-bus";
186 arm,vexpress,config-bridge = <&v2m_sysreg>;
190 compatible = "arm,vexpress-osc";
191 arm,vexpress-sysreg,func = <1 0>;
192 freq-range = <30000000 50000000>;
193 #clock-cells = <0>;
194 clock-output-names = "extsaxiclk";
199 compatible = "arm,vexpress-osc";
200 arm,vexpress-sysreg,func = <1 1>;
201 freq-range = <10000000 80000000>;
202 #clock-cells = <0>;
203 clock-output-names = "clcdclk";
208 compatible = "arm,vexpress-osc";
209 arm,vexpress-sysreg,func = <1 2>;
210 freq-range = <33000000 100000000>;
211 #clock-cells = <0>;
212 clock-output-names = "tcrefclk";
215 volt-vd10 {
217 compatible = "arm,vexpress-volt";
218 arm,vexpress-sysreg,func = <2 0>;
219 regulator-name = "VD10";
220 regulator-always-on;
224 volt-vd10-s2 {
226 compatible = "arm,vexpress-volt";
227 arm,vexpress-sysreg,func = <2 1>;
228 regulator-name = "VD10_S2";
229 regulator-always-on;
233 volt-vd10-s3 {
234 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
235 compatible = "arm,vexpress-volt";
236 arm,vexpress-sysreg,func = <2 2>;
237 regulator-name = "VD10_S3";
238 regulator-always-on;
242 volt-vcc1v8 {
244 compatible = "arm,vexpress-volt";
245 arm,vexpress-sysreg,func = <2 3>;
246 regulator-name = "VCC1V8";
247 regulator-always-on;
251 volt-ddr2vtt {
253 compatible = "arm,vexpress-volt";
254 arm,vexpress-sysreg,func = <2 4>;
255 regulator-name = "DDR2VTT";
256 regulator-always-on;
260 volt-vcc3v3 {
262 arm,vexpress-sysreg,func = <2 5>;
263 compatible = "arm,vexpress-volt";
264 regulator-name = "VCC3V3";
265 regulator-always-on;
269 amp-vd10-s2 {
271 compatible = "arm,vexpress-amp";
272 arm,vexpress-sysreg,func = <3 0>;
276 amp-vd10-s3 {
277 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
278 compatible = "arm,vexpress-amp";
279 arm,vexpress-sysreg,func = <3 1>;
283 power-vd10-s2 {
285 compatible = "arm,vexpress-power";
286 arm,vexpress-sysreg,func = <12 0>;
290 power-vd10-s3 {
291 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
292 compatible = "arm,vexpress-power";
293 arm,vexpress-sysreg,func = <12 1>;
299 compatible = "simple-bus";
301 #address-cells = <2>;
302 #size-cells = <1>;
309 #interrupt-cells = <1>;
310 interrupt-map-mask = <0 0 63>;
311 interrupt-map = <0 0 0 &gic 0 0 4>,
312 <0 0 1 &gic 0 1 4>,
313 <0 0 2 &gic 0 2 4>,
314 <0 0 3 &gic 0 3 4>,
315 <0 0 4 &gic 0 4 4>,
316 <0 0 5 &gic 0 5 4>,
317 <0 0 6 &gic 0 6 4>,
318 <0 0 7 &gic 0 7 4>,
319 <0 0 8 &gic 0 8 4>,
320 <0 0 9 &gic 0 9 4>,
321 <0 0 10 &gic 0 10 4>,
322 <0 0 11 &gic 0 11 4>,
323 <0 0 12 &gic 0 12 4>,
324 <0 0 13 &gic 0 13 4>,
325 <0 0 14 &gic 0 14 4>,
326 <0 0 15 &gic 0 15 4>,
327 <0 0 16 &gic 0 16 4>,
328 <0 0 17 &gic 0 17 4>,
329 <0 0 18 &gic 0 18 4>,
330 <0 0 19 &gic 0 19 4>,
331 <0 0 20 &gic 0 20 4>,
332 <0 0 21 &gic 0 21 4>,
333 <0 0 22 &gic 0 22 4>,
334 <0 0 23 &gic 0 23 4>,
335 <0 0 24 &gic 0 24 4>,
336 <0 0 25 &gic 0 25 4>,
337 <0 0 26 &gic 0 26 4>,
338 <0 0 27 &gic 0 27 4>,
339 <0 0 28 &gic 0 28 4>,
340 <0 0 29 &gic 0 29 4>,
341 <0 0 30 &gic 0 30 4>,
342 <0 0 31 &gic 0 31 4>,
343 <0 0 32 &gic 0 32 4>,
344 <0 0 33 &gic 0 33 4>,
345 <0 0 34 &gic 0 34 4>,
346 <0 0 35 &gic 0 35 4>,
347 <0 0 36 &gic 0 36 4>,
348 <0 0 37 &gic 0 37 4>,
349 <0 0 38 &gic 0 38 4>,
350 <0 0 39 &gic 0 39 4>,
351 <0 0 40 &gic 0 40 4>,
352 <0 0 41 &gic 0 41 4>,
353 <0 0 42 &gic 0 42 4>;
357 compatible = "simple-bus";
358 #address-cells = <1>;
359 #size-cells = <1>;
361 #interrupt-cells = <1>;
362 interrupt-map-mask = <0 3>;
363 interrupt-map = <0 0 &gic 0 36 4>,
364 <0 1 &gic 0 37 4>,
365 <0 2 &gic 0 38 4>,
366 <0 3 &gic 0 39 4>;