Lines Matching +full:reg +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
17 reg = <0 0>;
21 compatible = "mmio-sram";
22 reg = <0x40000000 0x40000>;
23 #address-cells = <1>;
24 #size-cells = <1>;
28 reg = <0x400 0x3fc00>;
34 compatible = "nvidia,tegra20-host1x";
35 reg = <0x50000000 0x00024000>;
38 interrupt-names = "syncpt", "host1x";
40 clock-names = "host1x";
42 reset-names = "host1x";
44 #address-cells = <1>;
45 #size-cells = <1>;
50 compatible = "nvidia,tegra20-mpe";
51 reg = <0x54040000 0x00040000>;
55 reset-names = "mpe";
59 compatible = "nvidia,tegra20-vi";
60 reg = <0x54080000 0x00040000>;
64 reset-names = "vi";
68 compatible = "nvidia,tegra20-epp";
69 reg = <0x540c0000 0x00040000>;
73 reset-names = "epp";
77 compatible = "nvidia,tegra20-isp";
78 reg = <0x54100000 0x00040000>;
82 reset-names = "isp";
86 compatible = "nvidia,tegra20-gr2d";
87 reg = <0x54140000 0x00040000>;
91 reset-names = "2d";
95 compatible = "nvidia,tegra20-gr3d";
96 reg = <0x54180000 0x00040000>;
99 reset-names = "3d";
103 compatible = "nvidia,tegra20-dc";
104 reg = <0x54200000 0x00040000>;
108 clock-names = "dc", "parent";
110 reset-names = "dc";
120 compatible = "nvidia,tegra20-dc";
121 reg = <0x54240000 0x00040000>;
125 clock-names = "dc", "parent";
127 reset-names = "dc";
137 compatible = "nvidia,tegra20-hdmi";
138 reg = <0x54280000 0x00040000>;
142 clock-names = "hdmi", "parent";
144 reset-names = "hdmi";
149 compatible = "nvidia,tegra20-tvo";
150 reg = <0x542c0000 0x00040000>;
157 compatible = "nvidia,tegra20-dsi";
158 reg = <0x54300000 0x00040000>;
161 clock-names = "dsi", "parent";
163 reset-names = "dsi";
169 compatible = "arm,cortex-a9-twd-timer";
170 interrupt-parent = <&intc>;
171 reg = <0x50040600 0x20>;
177 intc: interrupt-controller@50041000 {
178 compatible = "arm,cortex-a9-gic";
179 reg = <0x50041000 0x1000>,
181 interrupt-controller;
182 #interrupt-cells = <3>;
183 interrupt-parent = <&intc>;
186 cache-controller@50043000 {
187 compatible = "arm,pl310-cache";
188 reg = <0x50043000 0x1000>;
189 arm,data-latency = <5 5 2>;
190 arm,tag-latency = <4 4 2>;
191 cache-unified;
192 cache-level = <2>;
195 lic: interrupt-controller@60004000 {
196 compatible = "nvidia,tegra20-ictlr";
197 reg = <0x60004000 0x100>,
201 interrupt-controller;
202 #interrupt-cells = <3>;
203 interrupt-parent = <&intc>;
207 compatible = "nvidia,tegra20-timer";
208 reg = <0x60005000 0x60>;
217 compatible = "nvidia,tegra20-car";
218 reg = <0x60006000 0x1000>;
219 #clock-cells = <1>;
220 #reset-cells = <1>;
223 flow-controller@60007000 {
224 compatible = "nvidia,tegra20-flowctrl";
225 reg = <0x60007000 0x1000>;
229 compatible = "nvidia,tegra20-apbdma";
230 reg = <0x6000a000 0x1200>;
249 reset-names = "dma";
250 #dma-cells = <1>;
254 compatible = "nvidia,tegra20-ahb";
255 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
259 compatible = "nvidia,tegra20-gpio";
260 reg = <0x6000d000 0x1000>;
268 #gpio-cells = <2>;
269 gpio-controller;
270 #interrupt-cells = <2>;
271 interrupt-controller;
273 gpio-ranges = <&pinmux 0 0 224>;
278 compatible = "nvidia,tegra20-vde";
279 reg = <0x6001a000 0x1000>, /* Syntax Engine */
282 <0x6001c200 0x100>, /* Post-processing Engine */
288 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
292 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
294 interrupt-names = "sync-token", "bsev", "sxe";
296 reset-names = "vde", "mc";
301 compatible = "nvidia,tegra20-apbmisc";
302 reg = <0x70000800 0x64>, /* Chip revision */
307 compatible = "nvidia,tegra20-pinmux";
308 reg = <0x70000014 0x10>, /* Tri-state registers */
310 <0x700000a0 0x14>, /* Pull-up/down registers */
315 compatible = "nvidia,tegra20-das";
316 reg = <0x70000c00 0x80>;
320 compatible = "nvidia,tegra20-ac97";
321 reg = <0x70002000 0x200>;
325 reset-names = "ac97";
327 dma-names = "rx", "tx";
332 compatible = "nvidia,tegra20-i2s";
333 reg = <0x70002800 0x200>;
337 reset-names = "i2s";
339 dma-names = "rx", "tx";
344 compatible = "nvidia,tegra20-i2s";
345 reg = <0x70002a00 0x200>;
349 reset-names = "i2s";
351 dma-names = "rx", "tx";
359 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
360 * driver, the compatible is "nvidia,tegra20-hsuart".
363 compatible = "nvidia,tegra20-uart";
364 reg = <0x70006000 0x40>;
365 reg-shift = <2>;
369 reset-names = "serial";
371 dma-names = "rx", "tx";
376 compatible = "nvidia,tegra20-uart";
377 reg = <0x70006040 0x40>;
378 reg-shift = <2>;
382 reset-names = "serial";
384 dma-names = "rx", "tx";
389 compatible = "nvidia,tegra20-uart";
390 reg = <0x70006200 0x100>;
391 reg-shift = <2>;
395 reset-names = "serial";
397 dma-names = "rx", "tx";
402 compatible = "nvidia,tegra20-uart";
403 reg = <0x70006300 0x100>;
404 reg-shift = <2>;
408 reset-names = "serial";
410 dma-names = "rx", "tx";
415 compatible = "nvidia,tegra20-uart";
416 reg = <0x70006400 0x100>;
417 reg-shift = <2>;
421 reset-names = "serial";
423 dma-names = "rx", "tx";
427 nand-controller@70008000 {
428 compatible = "nvidia,tegra20-nand";
429 reg = <0x70008000 0x100>;
430 #address-cells = <1>;
431 #size-cells = <0>;
434 clock-names = "nand";
436 reset-names = "nand";
437 assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
438 assigned-clock-rates = <150000000>;
443 compatible = "nvidia,tegra20-gmi";
444 reg = <0x70009000 0x1000>;
445 #address-cells = <2>;
446 #size-cells = <1>;
449 clock-names = "gmi";
451 reset-names = "gmi";
456 compatible = "nvidia,tegra20-pwm";
457 reg = <0x7000a000 0x100>;
458 #pwm-cells = <2>;
461 reset-names = "pwm";
466 compatible = "nvidia,tegra20-rtc";
467 reg = <0x7000e000 0x100>;
473 compatible = "nvidia,tegra20-i2c";
474 reg = <0x7000c000 0x100>;
476 #address-cells = <1>;
477 #size-cells = <0>;
480 clock-names = "div-clk", "fast-clk";
482 reset-names = "i2c";
484 dma-names = "rx", "tx";
489 compatible = "nvidia,tegra20-sflash";
490 reg = <0x7000c380 0x80>;
492 #address-cells = <1>;
493 #size-cells = <0>;
496 reset-names = "spi";
498 dma-names = "rx", "tx";
503 compatible = "nvidia,tegra20-i2c";
504 reg = <0x7000c400 0x100>;
506 #address-cells = <1>;
507 #size-cells = <0>;
510 clock-names = "div-clk", "fast-clk";
512 reset-names = "i2c";
514 dma-names = "rx", "tx";
519 compatible = "nvidia,tegra20-i2c";
520 reg = <0x7000c500 0x100>;
522 #address-cells = <1>;
523 #size-cells = <0>;
526 clock-names = "div-clk", "fast-clk";
528 reset-names = "i2c";
530 dma-names = "rx", "tx";
535 compatible = "nvidia,tegra20-i2c-dvc";
536 reg = <0x7000d000 0x200>;
538 #address-cells = <1>;
539 #size-cells = <0>;
542 clock-names = "div-clk", "fast-clk";
544 reset-names = "i2c";
546 dma-names = "rx", "tx";
551 compatible = "nvidia,tegra20-slink";
552 reg = <0x7000d400 0x200>;
554 #address-cells = <1>;
555 #size-cells = <0>;
558 reset-names = "spi";
560 dma-names = "rx", "tx";
565 compatible = "nvidia,tegra20-slink";
566 reg = <0x7000d600 0x200>;
568 #address-cells = <1>;
569 #size-cells = <0>;
572 reset-names = "spi";
574 dma-names = "rx", "tx";
579 compatible = "nvidia,tegra20-slink";
580 reg = <0x7000d800 0x200>;
582 #address-cells = <1>;
583 #size-cells = <0>;
586 reset-names = "spi";
588 dma-names = "rx", "tx";
593 compatible = "nvidia,tegra20-slink";
594 reg = <0x7000da00 0x200>;
596 #address-cells = <1>;
597 #size-cells = <0>;
600 reset-names = "spi";
602 dma-names = "rx", "tx";
607 compatible = "nvidia,tegra20-kbc";
608 reg = <0x7000e200 0x100>;
612 reset-names = "kbc";
617 compatible = "nvidia,tegra20-pmc";
618 reg = <0x7000e400 0x400>;
620 clock-names = "pclk", "clk32k_in";
621 #clock-cells = <1>;
624 mc: memory-controller@7000f000 {
625 compatible = "nvidia,tegra20-mc-gart";
626 reg = <0x7000f000 0x00000400>, /* controller registers */
629 clock-names = "mc";
631 #reset-cells = <1>;
632 #iommu-cells = <0>;
635 memory-controller@7000f400 {
636 compatible = "nvidia,tegra20-emc";
637 reg = <0x7000f400 0x200>;
640 #address-cells = <1>;
641 #size-cells = <0>;
645 compatible = "nvidia,tegra20-efuse";
646 reg = <0x7000f800 0x400>;
648 clock-names = "fuse";
650 reset-names = "fuse";
654 compatible = "nvidia,tegra20-pcie";
656 reg = <0x80003000 0x00000800>, /* PADS registers */
659 reg-names = "pads", "afi", "cs";
662 interrupt-names = "intr", "msi";
664 #interrupt-cells = <1>;
665 interrupt-map-mask = <0 0 0 0>;
666 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
668 bus-range = <0x00 0xff>;
669 #address-cells = <3>;
670 #size-cells = <2>;
675 <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */
681 clock-names = "pex", "afi", "pll_e";
685 reset-names = "pex", "afi", "pcie_x";
690 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
691 reg = <0x000800 0 0 0 0>;
692 bus-range = <0x00 0xff>;
695 #address-cells = <3>;
696 #size-cells = <2>;
699 nvidia,num-lanes = <2>;
704 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
705 reg = <0x001000 0 0 0 0>;
706 bus-range = <0x00 0xff>;
709 #address-cells = <3>;
710 #size-cells = <2>;
713 nvidia,num-lanes = <2>;
718 compatible = "nvidia,tegra20-ehci", "usb-ehci";
719 reg = <0xc5000000 0x4000>;
722 nvidia,has-legacy-mode;
725 reset-names = "usb";
726 nvidia,needs-double-reset;
731 phy1: usb-phy@c5000000 {
732 compatible = "nvidia,tegra20-usb-phy";
733 reg = <0xc5000000 0x4000>,
740 clock-names = "reg", "pll_u", "timer", "utmi-pads";
742 reset-names = "usb", "utmi-pads";
743 #phy-cells = <0>;
744 nvidia,has-legacy-mode;
745 nvidia,hssync-start-delay = <9>;
746 nvidia,idle-wait-delay = <17>;
747 nvidia,elastic-limit = <16>;
748 nvidia,term-range-adj = <6>;
749 nvidia,xcvr-setup = <9>;
750 nvidia,xcvr-lsfslew = <1>;
751 nvidia,xcvr-lsrslew = <1>;
752 nvidia,has-utmi-pad-registers;
757 compatible = "nvidia,tegra20-ehci", "usb-ehci";
758 reg = <0xc5004000 0x4000>;
763 reset-names = "usb";
768 phy2: usb-phy@c5004000 {
769 compatible = "nvidia,tegra20-usb-phy";
770 reg = <0xc5004000 0x4000>;
775 clock-names = "reg", "pll_u", "ulpi-link";
777 reset-names = "usb", "utmi-pads";
778 #phy-cells = <0>;
783 compatible = "nvidia,tegra20-ehci", "usb-ehci";
784 reg = <0xc5008000 0x4000>;
789 reset-names = "usb";
794 phy3: usb-phy@c5008000 {
795 compatible = "nvidia,tegra20-usb-phy";
796 reg = <0xc5008000 0x4000>,
803 clock-names = "reg", "pll_u", "timer", "utmi-pads";
805 reset-names = "usb", "utmi-pads";
806 #phy-cells = <0>;
807 nvidia,hssync-start-delay = <9>;
808 nvidia,idle-wait-delay = <17>;
809 nvidia,elastic-limit = <16>;
810 nvidia,term-range-adj = <6>;
811 nvidia,xcvr-setup = <9>;
812 nvidia,xcvr-lsfslew = <2>;
813 nvidia,xcvr-lsrslew = <2>;
818 compatible = "nvidia,tegra20-sdhci";
819 reg = <0xc8000000 0x200>;
822 clock-names = "sdhci";
824 reset-names = "sdhci";
829 compatible = "nvidia,tegra20-sdhci";
830 reg = <0xc8000200 0x200>;
833 clock-names = "sdhci";
835 reset-names = "sdhci";
840 compatible = "nvidia,tegra20-sdhci";
841 reg = <0xc8000400 0x200>;
844 clock-names = "sdhci";
846 reset-names = "sdhci";
851 compatible = "nvidia,tegra20-sdhci";
852 reg = <0xc8000600 0x200>;
855 clock-names = "sdhci";
857 reset-names = "sdhci";
862 #address-cells = <1>;
863 #size-cells = <0>;
867 compatible = "arm,cortex-a9";
868 reg = <0>;
874 compatible = "arm,cortex-a9";
875 reg = <1>;
881 compatible = "arm,cortex-a9-pmu";
884 interrupt-affinity = <&{/cpus/cpu@0}>,