Lines Matching +full:0 +full:x7000a000
19 reg = <0x0 0x80000000 0x0 0x0>;
25 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
26 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
27 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
34 interrupt-map-mask = <0 0 0 0>;
35 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
37 bus-range = <0x00 0xff>;
41 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
42 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
43 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
44 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
45 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
58 pci@1,0 {
60 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
61 reg = <0x000800 0 0 0 0>;
62 bus-range = <0x00 0xff>;
72 pci@2,0 {
74 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
75 reg = <0x001000 0 0 0 0>;
76 bus-range = <0x00 0xff>;
89 reg = <0x0 0x50000000 0x0 0x00034000>;
102 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
106 reg = <0x0 0x54200000 0x0 0x00040000>;
115 nvidia,head = <0>;
120 reg = <0x0 0x54240000 0x0 0x00040000>;
134 reg = <0x0 0x54280000 0x0 0x00040000>;
146 reg = <0x0 0x54340000 0x0 0x00040000>;
158 reg = <0x0 0x54540000 0x0 0x00040000>;
173 reg = <0x0 0x545c0000 0x0 0x00040000>;
184 #size-cells = <0>;
193 reg = <0x0 0x50041000 0x0 0x1000>,
194 <0x0 0x50042000 0x0 0x1000>,
195 <0x0 0x50044000 0x0 0x2000>,
196 <0x0 0x50046000 0x0 0x2000>;
203 * Please keep the following 0, notation in place as a former mainline
207 gpu@0,57000000 {
209 reg = <0x0 0x57000000 0x0 0x01000000>,
210 <0x0 0x58000000 0x0 0x01000000>;
227 reg = <0x0 0x60004000 0x0 0x100>,
228 <0x0 0x60004100 0x0 0x100>,
229 <0x0 0x60004200 0x0 0x100>,
230 <0x0 0x60004300 0x0 0x100>,
231 <0x0 0x60004400 0x0 0x100>;
239 reg = <0x0 0x60005000 0x0 0x400>;
240 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
251 reg = <0x0 0x60006000 0x0 0x1000>;
259 reg = <0x0 0x60007000 0x0 0x1000>;
264 reg = <0x0 0x6000c800 0x0 0x400>;
275 reg = <0x0 0x6000d000 0x0 0x1000>;
289 gpio-ranges = <&pinmux 0 0 251>;
295 reg = <0x0 0x60020000 0x0 0x1400>;
336 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
337 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
342 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
343 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
344 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
357 reg = <0x0 0x70006000 0x0 0x40>;
370 reg = <0x0 0x70006040 0x0 0x40>;
383 reg = <0x0 0x70006200 0x0 0x40>;
396 reg = <0x0 0x70006300 0x0 0x40>;
409 reg = <0x0 0x7000a000 0x0 0x100>;
419 reg = <0x0 0x7000c000 0x0 0x100>;
422 #size-cells = <0>;
434 reg = <0x0 0x7000c400 0x0 0x100>;
437 #size-cells = <0>;
449 reg = <0x0 0x7000c500 0x0 0x100>;
452 #size-cells = <0>;
464 reg = <0x0 0x7000c700 0x0 0x100>;
467 #size-cells = <0>;
479 reg = <0x0 0x7000d000 0x0 0x100>;
482 #size-cells = <0>;
494 reg = <0x0 0x7000d100 0x0 0x100>;
497 #size-cells = <0>;
509 reg = <0x0 0x7000d400 0x0 0x200>;
512 #size-cells = <0>;
524 reg = <0x0 0x7000d600 0x0 0x200>;
527 #size-cells = <0>;
539 reg = <0x0 0x7000d800 0x0 0x200>;
542 #size-cells = <0>;
554 reg = <0x0 0x7000da00 0x0 0x200>;
557 #size-cells = <0>;
569 reg = <0x0 0x7000dc00 0x0 0x200>;
572 #size-cells = <0>;
584 reg = <0x0 0x7000de00 0x0 0x200>;
587 #size-cells = <0>;
599 reg = <0x0 0x7000e000 0x0 0x100>;
606 reg = <0x0 0x7000e400 0x0 0x400>;
614 reg = <0x0 0x7000f800 0x0 0x400>;
623 reg = <0x0 0x70019000 0x0 0x1000>;
635 reg = <0x0 0x7001b000 0x0 0x1000>;
644 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
645 <0x0 0x70020000 0x0 0x7000>; /* SATA */
661 reg = <0x0 0x70030000 0x0 0x10000>;
676 reg = <0x0 0x70090000 0x0 0x8000>,
677 <0x0 0x70098000 0x0 0x1000>,
678 <0x0 0x70099000 0x0 0x1000>;
711 reg = <0x0 0x7009f000 0x0 0x1000>;
720 usb2-0 {
722 #phy-cells = <0>;
727 #phy-cells = <0>;
732 #phy-cells = <0>;
741 ulpi-0 {
743 #phy-cells = <0>;
752 hsic-0 {
754 #phy-cells = <0>;
759 #phy-cells = <0>;
768 pcie-0 {
770 #phy-cells = <0>;
775 #phy-cells = <0>;
780 #phy-cells = <0>;
785 #phy-cells = <0>;
790 #phy-cells = <0>;
799 sata-0 {
801 #phy-cells = <0>;
808 usb2-0 {
820 ulpi-0 {
824 hsic-0 {
832 usb3-0 {
844 reg = <0x0 0x700b0000 0x0 0x200>;
855 reg = <0x0 0x700b0200 0x0 0x200>;
866 reg = <0x0 0x700b0400 0x0 0x200>;
877 reg = <0x0 0x700b0600 0x0 0x200>;
888 reg = <0x0 0x70015000 0x0 0x00001000>;
898 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
899 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
921 reg = <0 0x70110000 0 0x100>, /* DFLL control */
922 <0 0x70110000 0 0x100>, /* I2C output control */
923 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
924 <0 0x70110200 0 0x100>; /* Look-up table RAM */
932 #clock-cells = <0>;
935 nvidia,droop-ctrl = <0x00000f00>;
938 nvidia,ci = <0>;
945 reg = <0x0 0x70300000 0x0 0x200>,
946 <0x0 0x70300800 0x0 0x800>,
947 <0x0 0x70300200 0x0 0x600>;
997 reg = <0x0 0x70301000 0x0 0x100>;
1007 reg = <0x0 0x70301100 0x0 0x100>;
1017 reg = <0x0 0x70301200 0x0 0x100>;
1027 reg = <0x0 0x70301300 0x0 0x100>;
1037 reg = <0x0 0x70301400 0x0 0x100>;
1048 reg = <0x0 0x7d000000 0x0 0x4000>;
1060 reg = <0x0 0x7d000000 0x0 0x4000>,
1061 <0x0 0x7d000000 0x0 0x4000>;
1069 #phy-cells = <0>;
1070 nvidia,hssync-start-delay = <0>;
1075 nvidia,xcvr-lsfslew = <0>;
1086 reg = <0x0 0x7d004000 0x0 0x4000>;
1098 reg = <0x0 0x7d004000 0x0 0x4000>,
1099 <0x0 0x7d000000 0x0 0x4000>;
1107 #phy-cells = <0>;
1108 nvidia,hssync-start-delay = <0>;
1113 nvidia,xcvr-lsfslew = <0>;
1123 reg = <0x0 0x7d008000 0x0 0x4000>;
1135 reg = <0x0 0x7d008000 0x0 0x4000>,
1136 <0x0 0x7d000000 0x0 0x4000>;
1144 #phy-cells = <0>;
1145 nvidia,hssync-start-delay = <0>;
1150 nvidia,xcvr-lsfslew = <0>;
1160 #size-cells = <0>;
1162 cpu@0 {
1165 reg = <0>;
1202 interrupt-affinity = <&{/cpus/cpu@0}>,
1219 hysteresis = <0>;
1247 hysteresis = <0>;
1270 hysteresis = <0>;
1298 hysteresis = <0>;