Lines Matching +full:0 +full:x7000a000
17 reg = <0x80000000 0x0>;
22 reg = <0x50000000 0x00028000>;
35 ranges = <0x54000000 0x54000000 0x01000000>;
39 reg = <0x54140000 0x00040000>;
50 reg = <0x54180000 0x00040000>;
60 reg = <0x54200000 0x00040000>;
70 nvidia,head = <0>;
79 reg = <0x54240000 0x00040000>;
98 reg = <0x54280000 0x00040000>;
110 reg = <0x54300000 0x00040000>;
117 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
121 #size-cells = <0>;
126 reg = <0x54400000 0x00040000>;
133 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
137 #size-cells = <0>;
145 reg = <0x50041000 0x1000>,
146 <0x50042000 0x1000>,
147 <0x50044000 0x2000>,
148 <0x50046000 0x2000>;
156 reg = <0x60004000 0x100>,
157 <0x60004100 0x50>,
158 <0x60004200 0x50>,
159 <0x60004300 0x50>,
160 <0x60004400 0x50>;
168 reg = <0x60005000 0x400>;
169 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
180 reg = <0x60006000 0x1000>;
187 reg = <0x60007000 0x1000>;
192 reg = <0x6000a000 0x1400>;
233 reg = <0x6000c000 0x150>;
238 reg = <0x6000d000 0x1000>;
252 gpio-ranges = <&pinmux 0 0 246>;
258 reg = <0x70000800 0x64>, /* Chip revision */
259 <0x70000008 0x04>; /* Strapping options */
264 reg = <0x70000868 0x148>, /* Pad control registers */
265 <0x70003000 0x40c>; /* Mux registers */
278 reg = <0x70006000 0x40>;
291 reg = <0x70006040 0x40>;
304 reg = <0x70006200 0x100>;
317 reg = <0x70006300 0x100>;
330 reg = <0x7000a000 0x100>;
340 reg = <0x7000c000 0x100>;
343 #size-cells = <0>;
355 reg = <0x7000c400 0x100>;
358 #size-cells = <0>;
370 reg = <0x7000c500 0x100>;
373 #size-cells = <0>;
385 reg = <0x7000c700 0x100>;
388 #size-cells = <0>;
400 reg = <0x7000d000 0x100>;
403 #size-cells = <0>;
415 reg = <0x7000d400 0x200>;
418 #size-cells = <0>;
430 reg = <0x7000d600 0x200>;
433 #size-cells = <0>;
445 reg = <0x7000d800 0x200>;
448 #size-cells = <0>;
460 reg = <0x7000da00 0x200>;
463 #size-cells = <0>;
475 reg = <0x7000dc00 0x200>;
478 #size-cells = <0>;
490 reg = <0x7000de00 0x200>;
493 #size-cells = <0>;
505 reg = <0x7000e000 0x100>;
512 reg = <0x7000e200 0x100>;
522 reg = <0x7000e400 0x400>;
530 reg = <0x7000f800 0x400>;
539 reg = <0x70019000 0x1000>;
550 reg = <0x70080000 0x200>,
551 <0x70080200 0x100>,
552 <0x70081000 0x200>;
593 reg = <0x70080300 0x100>;
603 reg = <0x70080400 0x100>;
613 reg = <0x70080500 0x100>;
623 reg = <0x70080600 0x100>;
633 reg = <0x70080700 0x100>;
644 reg = <0x700e3000 0x100>;
651 reg = <0x78000000 0x200>;
662 reg = <0x78000200 0x200>;
673 reg = <0x78000400 0x200>;
684 reg = <0x78000600 0x200>;
695 reg = <0x7d000000 0x4000>;
707 reg = <0x7d000000 0x4000>,
708 <0x7d000000 0x4000>;
716 #phy-cells = <0>;
717 nvidia,hssync-start-delay = <0>;
722 nvidia,xcvr-lsfslew = <0>;
733 reg = <0x7d008000 0x4000>;
745 reg = <0x7d008000 0x4000>,
746 <0x7d000000 0x4000>;
754 #phy-cells = <0>;
755 nvidia,hssync-start-delay = <0>;
760 nvidia,xcvr-lsfslew = <0>;
770 #size-cells = <0>;
772 cpu@0 {
775 reg = <0>;