boot/dts/suniv-f1c100s.dtsi

1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
3  * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
8 	#address-cells = <1>;
9 	#size-cells = <1>;
10 	interrupt-parent = <&intc>;
13 		osc24M: clk-24M {
14 			#clock-cells = <0>;
15 			compatible = "fixed-clock";
16 			clock-frequency = <24000000>;
17 			clock-output-names = "osc24M";
20 		osc32k: clk-32k {
21 			#clock-cells = <0>;
22 			compatible = "fixed-clock";
23 			clock-frequency = <32768>;
24 			clock-output-names = "osc32k";
30 			compatible = "arm,arm926ej-s";
36 		compatible = "simple-bus";
37 		#address-cells = <1>;
38 		#size-cells = <1>;
41 		sram-controller@1c00000 {
42 			compatible = "allwinner,suniv-f1c100s-system-control",
43 				     "allwinner,sun4i-a10-system-control";
44 			reg = <0x01c00000 0x30>;
45 			#address-cells = <1>;
46 			#size-cells = <1>;
50 				compatible = "mmio-sram";
51 				reg = <0x00010000 0x1000>;
52 				#address-cells = <1>;
53 				#size-cells = <1>;
56 				otg_sram: sram-section@0 {
57 					compatible = "allwinner,suniv-f1c100s-sram-d",
58 						     "allwinner,sun4i-a10-sram-d";
59 					reg = <0x0000 0x1000>;
66 			compatible = "allwinner,suniv-f1c100s-ccu";
67 			reg = <0x01c20000 0x400>;
69 			clock-names = "hosc", "losc";
70 			#clock-cells = <1>;
71 			#reset-cells = <1>;
74 		intc: interrupt-controller@1c20400 {
75 			compatible = "allwinner,suniv-f1c100s-ic";
76 			reg = <0x01c20400 0x400>;
77 			interrupt-controller;
78 			#interrupt-cells = <1>;
82 			compatible = "allwinner,suniv-f1c100s-pinctrl";
83 			reg = <0x01c20800 0x400>;
86 			clock-names = "apb", "hosc", "losc";
87 			gpio-controller;
88 			interrupt-controller;
89 			#interrupt-cells = <3>;
90 			#gpio-cells = <3>;
92 			uart0_pe_pins: uart0-pe-pins {
99 			compatible = "allwinner,suniv-f1c100s-timer";
100 			reg = <0x01c20c00 0x90>;
106 			compatible = "allwinner,suniv-f1c100s-wdt",
107 				     "allwinner,sun4i-a10-wdt";
108 			reg = <0x01c20ca0 0x20>;
112 			compatible = "snps,dw-apb-uart";
113 			reg = <0x01c25000 0x400>;
115 			reg-shift = <2>;
116 			reg-io-width = <4>;
123 			compatible = "snps,dw-apb-uart";
124 			reg = <0x01c25400 0x400>;
126 			reg-shift = <2>;
127 			reg-io-width = <4>;
134 			compatible = "snps,dw-apb-uart";
135 			reg = <0x01c25800 0x400>;
137 			reg-shift = <2>;
138 			reg-io-width = <4>;