boot/dts/sun4i-a10.dtsi

46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
67 			clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
68 				 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
69 				 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
77 			clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
78 				 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
79 				 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
80 				 <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
81 				 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
89 			clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
90 				 <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>,
91 				 <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>,
92 				 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
100 			clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
101 				 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
102 				 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
103 				 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>,
104 				 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
116 			clocks = <&ccu CLK_CPU>;
266 			clocks = <&ccu CLK_AHB_DMA>;
274 			clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
287 			clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
301 			clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
317 			clocks = <&ccu CLK_AHB_EMAC>;
336 			resets = <&ccu RST_TCON0>;
338 			clocks = <&ccu CLK_AHB_LCD0>,
339 				 <&ccu CLK_TCON0_CH0>,
340 				 <&ccu CLK_TCON0_CH1>;
386 			resets = <&ccu RST_TCON1>;
388 			clocks = <&ccu CLK_AHB_LCD1>,
389 				 <&ccu CLK_TCON1_CH0>,
390 				 <&ccu CLK_TCON1_CH1>;
435 			clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
436 				 <&ccu CLK_DRAM_VE>;
438 			resets = <&ccu RST_VE>;
446 			clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
459 			clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
470 			clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
481 			clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>;
492 			clocks = <&ccu CLK_AHB_OTG>;
508 			clocks = <&ccu CLK_USB_PHY>;
510 			resets = <&ccu RST_USB_PHY0>,
511 				 <&ccu RST_USB_PHY1>,
512 				 <&ccu RST_USB_PHY2>;
521 			clocks = <&ccu CLK_AHB_EHCI0>;
531 			clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
541 			clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
549 			clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
550 				 <&ccu CLK_PLL_VIDEO0_2X>,
551 				 <&ccu CLK_PLL_VIDEO1_2X>;
589 			clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
603 			clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
611 			clocks = <&ccu CLK_AHB_EHCI1>;
621 			clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
631 			clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
633 			resets = <&ccu RST_CSI1>;
641 			clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
651 		ccu: clock@1c20000 {  label
652 			compatible = "allwinner,sun4i-a10-ccu";
671 			clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
880 			clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
890 			clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
899 			clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
911 			clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
931 			clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
957 			clocks = <&ccu CLK_APB1_UART0>;
967 			clocks = <&ccu CLK_APB1_UART1>;
977 			clocks = <&ccu CLK_APB1_UART2>;
987 			clocks = <&ccu CLK_APB1_UART3>;
997 			clocks = <&ccu CLK_APB1_UART4>;
1007 			clocks = <&ccu CLK_APB1_UART5>;
1017 			clocks = <&ccu CLK_APB1_UART6>;
1027 			clocks = <&ccu CLK_APB1_UART7>;
1035 			clocks = <&ccu CLK_APB1_PS20>;
1043 			clocks = <&ccu CLK_APB1_PS21>;
1051 			clocks = <&ccu CLK_APB1_I2C0>;
1063 			clocks = <&ccu CLK_APB1_I2C1>;
1075 			clocks = <&ccu CLK_APB1_I2C2>;
1087 			clocks = <&ccu CLK_APB1_CAN>;
1104 			clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1106 			resets = <&ccu RST_GPU>;
1108 			assigned-clocks = <&ccu CLK_GPU>;
1116 			clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1117 				 <&ccu CLK_DRAM_DE_FE0>;
1120 			resets = <&ccu RST_DE_FE0>;
1148 			clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1149 				 <&ccu CLK_DRAM_DE_FE1>;
1152 			resets = <&ccu RST_DE_FE1>;
1180 			clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1181 				 <&ccu CLK_DRAM_DE_BE1>;
1184 			resets = <&ccu RST_DE_BE1>;
1228 			clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1229 				 <&ccu CLK_DRAM_DE_BE0>;
1232 			resets = <&ccu RST_DE_BE0>;