Lines Matching +full:0 +full:x400
54 #clock-cells = <0>;
56 clock-frequency = <0>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
68 clock-frequency = <0>;
75 reg = <0x40000c00 0x400>;
82 #size-cells = <0>;
84 reg = <0x40002400 0x400>;
95 trigger@0 {
97 reg = <0>;
109 #size-cells = <0>;
111 reg = <0x40003800 0x400>;
121 #size-cells = <0>;
123 reg = <0x40003c00 0x400>;
132 reg = <0x40004400 0x400>;
141 #size-cells = <0>;
142 reg = <0x40005400 0x400>;
153 #size-cells = <0>;
154 reg = <0x40005800 0x400>;
165 #size-cells = <0>;
166 reg = <0x40005C00 0x400>;
176 reg = <0x40007400 0x400>;
180 #size-cells = <0>;
200 reg = <0x40011000 0x400>;
208 #size-cells = <0>;
210 reg = <0x40013000 0x400>;
219 #size-cells = <0>;
221 reg = <0x40013400 0x400>;
230 #size-cells = <0>;
232 reg = <0x40015000 0x400>;
241 reg = <0x40020000 0x400>;
259 reg = <0x40020400 0x400>;
277 reg = <0x40020800 0x1c>;
287 reg = <0x40022000 0x400>;
294 #size-cells = <0>;
297 adc1: adc@0 {
300 reg = <0x0>;
302 interrupts = <0>;
309 reg = <0x100>;
318 reg = <0x40040000 0x40000>;
330 reg = <0x40080000 0x40000>;
339 reg = <0x50001000 0x200>;
349 reg = <0x52000000 0x1000>;
359 arm,primecell-periphid = <0x10153180>;
360 reg = <0x52007000 0x1000>;
375 reg = <0x58000000 0x400>;
381 reg = <0x58000400 0x400>;
386 #size-cells = <0>;
388 reg = <0x58001400 0x400>;
398 #size-cells = <0>;
399 reg = <0x58001C00 0x400>;
409 #size-cells = <0>;
411 reg = <0x58002400 0x400>;
436 #size-cells = <0>;
438 reg = <0x58002800 0x400>;
458 #size-cells = <0>;
460 reg = <0x58002c00 0x400>;
474 #size-cells = <0>;
476 reg = <0x58003000 0x400>;
490 reg = <0x58003C00 0x8>;
499 reg = <0x58004000 0x400>;
506 st,syscfg = <&pwrcfg 0x00 0x100>;
512 reg = <0x58024400 0x400>;
521 reg = <0x58024800 0x400>;
526 reg = <0x58026000 0x400>;
533 #size-cells = <0>;
536 adc3: adc@0 {
539 reg = <0x0>;
541 interrupts = <0>;
548 reg = <0x40028000 0x8000>;
554 st,syscon = <&syscfg 0x4>;