Lines Matching +full:stm32 +full:- +full:timer +full:- +full:trigger
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
52 clk_hse: clk-hse {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
55 clock-frequency = <0>;
58 clk-lse {
59 #clock-cells = <0>;
60 compatible = "fixed-clock";
61 clock-frequency = <32768>;
64 clk-lsi {
65 #clock-cells = <0>;
66 compatible = "fixed-clock";
67 clock-frequency = <32000>;
70 clk_i2s_ckin: clk-i2s-ckin {
71 #clock-cells = <0>;
72 compatible = "fixed-clock";
73 clock-frequency = <48000000>;
78 timer2: timer@40000000 {
79 compatible = "st,stm32-timer";
87 #address-cells = <1>;
88 #size-cells = <0>;
89 compatible = "st,stm32-timers";
92 clock-names = "int";
96 compatible = "st,stm32-pwm";
97 #pwm-cells = <3>;
101 timer@1 {
102 compatible = "st,stm32-timer-trigger";
108 timer3: timer@40000400 {
109 compatible = "st,stm32-timer";
117 #address-cells = <1>;
118 #size-cells = <0>;
119 compatible = "st,stm32-timers";
122 clock-names = "int";
126 compatible = "st,stm32-pwm";
127 #pwm-cells = <3>;
131 timer@2 {
132 compatible = "st,stm32-timer-trigger";
138 timer4: timer@40000800 {
139 compatible = "st,stm32-timer";
147 #address-cells = <1>;
148 #size-cells = <0>;
149 compatible = "st,stm32-timers";
152 clock-names = "int";
156 compatible = "st,stm32-pwm";
157 #pwm-cells = <3>;
161 timer@3 {
162 compatible = "st,stm32-timer-trigger";
168 timer5: timer@40000c00 {
169 compatible = "st,stm32-timer";
176 #address-cells = <1>;
177 #size-cells = <0>;
178 compatible = "st,stm32-timers";
181 clock-names = "int";
185 compatible = "st,stm32-pwm";
186 #pwm-cells = <3>;
190 timer@4 {
191 compatible = "st,stm32-timer-trigger";
197 timer6: timer@40001000 {
198 compatible = "st,stm32-timer";
206 #address-cells = <1>;
207 #size-cells = <0>;
208 compatible = "st,stm32-timers";
211 clock-names = "int";
214 timer@5 {
215 compatible = "st,stm32-timer-trigger";
221 timer7: timer@40001400 {
222 compatible = "st,stm32-timer";
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "st,stm32-timers";
235 clock-names = "int";
238 timer@6 {
239 compatible = "st,stm32-timer-trigger";
246 #address-cells = <1>;
247 #size-cells = <0>;
248 compatible = "st,stm32-timers";
251 clock-names = "int";
255 compatible = "st,stm32-pwm";
256 #pwm-cells = <3>;
260 timer@11 {
261 compatible = "st,stm32-timer-trigger";
268 #address-cells = <1>;
269 #size-cells = <0>;
270 compatible = "st,stm32-timers";
273 clock-names = "int";
277 compatible = "st,stm32-pwm";
278 #pwm-cells = <3>;
284 #address-cells = <1>;
285 #size-cells = <0>;
286 compatible = "st,stm32-timers";
289 clock-names = "int";
293 compatible = "st,stm32-pwm";
294 #pwm-cells = <3>;
300 compatible = "st,stm32-rtc";
303 assigned-clocks = <&rcc 1 CLK_RTC>;
304 assigned-clock-parents = <&rcc 1 CLK_LSE>;
305 interrupt-parent = <&exti>;
312 compatible = "st,stm32f7-uart";
320 compatible = "st,stm32f7-uart";
328 compatible = "st,stm32f7-uart";
336 compatible = "st,stm32f7-uart";
344 compatible = "st,stm32f7-i2c";
350 #address-cells = <1>;
351 #size-cells = <0>;
356 compatible = "st,stm32f7-i2c";
362 #address-cells = <1>;
363 #size-cells = <0>;
368 compatible = "st,stm32f7-i2c";
374 #address-cells = <1>;
375 #size-cells = <0>;
380 compatible = "st,stm32f7-i2c";
386 #address-cells = <1>;
387 #size-cells = <0>;
392 compatible = "st,stm32-cec";
396 clock-names = "cec", "hdmi-cec";
401 compatible = "st,stm32f7-uart";
409 compatible = "st,stm32f7-uart";
417 #address-cells = <1>;
418 #size-cells = <0>;
419 compatible = "st,stm32-timers";
422 clock-names = "int";
426 compatible = "st,stm32-pwm";
427 #pwm-cells = <3>;
431 timer@0 {
432 compatible = "st,stm32-timer-trigger";
439 #address-cells = <1>;
440 #size-cells = <0>;
441 compatible = "st,stm32-timers";
444 clock-names = "int";
448 compatible = "st,stm32-pwm";
449 #pwm-cells = <3>;
453 timer@7 {
454 compatible = "st,stm32-timer-trigger";
461 compatible = "st,stm32f7-uart";
469 compatible = "st,stm32f7-uart";
478 arm,primecell-periphid = <0x00880180>;
481 clock-names = "apb_pclk";
483 max-frequency = <48000000>;
489 arm,primecell-periphid = <0x00880180>;
492 clock-names = "apb_pclk";
494 max-frequency = <48000000>;
499 compatible = "st,stm32-syscfg", "syscon";
503 exti: interrupt-controller@40013c00 {
504 compatible = "st,stm32-exti";
505 interrupt-controller;
506 #interrupt-cells = <2>;
512 #address-cells = <1>;
513 #size-cells = <0>;
514 compatible = "st,stm32-timers";
517 clock-names = "int";
521 compatible = "st,stm32-pwm";
522 #pwm-cells = <3>;
526 timer@8 {
527 compatible = "st,stm32-timer-trigger";
534 #address-cells = <1>;
535 #size-cells = <0>;
536 compatible = "st,stm32-timers";
539 clock-names = "int";
543 compatible = "st,stm32-pwm";
544 #pwm-cells = <3>;
550 #address-cells = <1>;
551 #size-cells = <0>;
552 compatible = "st,stm32-timers";
555 clock-names = "int";
559 compatible = "st,stm32-pwm";
560 #pwm-cells = <3>;
565 pwrcfg: power-config@40007000 {
566 compatible = "st,stm32-power-config", "syscon";
571 compatible = "st,stm32f7-crc";
578 #reset-cells = <1>;
579 #clock-cells = <2>;
580 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
584 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
585 assigned-clock-rates = <1000000>;
588 dma1: dma-controller@40026000 {
589 compatible = "st,stm32-dma";
600 #dma-cells = <4>;
604 dma2: dma-controller@40026400 {
605 compatible = "st,stm32-dma";
616 #dma-cells = <4>;
622 compatible = "st,stm32f7-hsotg";
626 clock-names = "otg";
627 g-rx-fifo-size = <256>;
628 g-np-tx-fifo-size = <32>;
629 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
634 compatible = "st,stm32f4x9-fsotg";
638 clock-names = "otg";