Lines Matching +full:reg +full:- +full:names
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
52 clk_hse: clk-hse {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
55 clock-frequency = <0>;
58 clk-lse {
59 #clock-cells = <0>;
60 compatible = "fixed-clock";
61 clock-frequency = <32768>;
64 clk-lsi {
65 #clock-cells = <0>;
66 compatible = "fixed-clock";
67 clock-frequency = <32000>;
70 clk_i2s_ckin: clk-i2s-ckin {
71 #clock-cells = <0>;
72 compatible = "fixed-clock";
73 clock-frequency = <48000000>;
79 compatible = "st,stm32-timer";
80 reg = <0x40000000 0x400>;
87 #address-cells = <1>;
88 #size-cells = <0>;
89 compatible = "st,stm32-timers";
90 reg = <0x40000000 0x400>;
92 clock-names = "int";
96 compatible = "st,stm32-pwm";
97 #pwm-cells = <3>;
102 compatible = "st,stm32-timer-trigger";
103 reg = <1>;
109 compatible = "st,stm32-timer";
110 reg = <0x40000400 0x400>;
117 #address-cells = <1>;
118 #size-cells = <0>;
119 compatible = "st,stm32-timers";
120 reg = <0x40000400 0x400>;
122 clock-names = "int";
126 compatible = "st,stm32-pwm";
127 #pwm-cells = <3>;
132 compatible = "st,stm32-timer-trigger";
133 reg = <2>;
139 compatible = "st,stm32-timer";
140 reg = <0x40000800 0x400>;
147 #address-cells = <1>;
148 #size-cells = <0>;
149 compatible = "st,stm32-timers";
150 reg = <0x40000800 0x400>;
152 clock-names = "int";
156 compatible = "st,stm32-pwm";
157 #pwm-cells = <3>;
162 compatible = "st,stm32-timer-trigger";
163 reg = <3>;
169 compatible = "st,stm32-timer";
170 reg = <0x40000c00 0x400>;
176 #address-cells = <1>;
177 #size-cells = <0>;
178 compatible = "st,stm32-timers";
179 reg = <0x40000C00 0x400>;
181 clock-names = "int";
185 compatible = "st,stm32-pwm";
186 #pwm-cells = <3>;
191 compatible = "st,stm32-timer-trigger";
192 reg = <4>;
198 compatible = "st,stm32-timer";
199 reg = <0x40001000 0x400>;
206 #address-cells = <1>;
207 #size-cells = <0>;
208 compatible = "st,stm32-timers";
209 reg = <0x40001000 0x400>;
211 clock-names = "int";
215 compatible = "st,stm32-timer-trigger";
216 reg = <5>;
222 compatible = "st,stm32-timer";
223 reg = <0x40001400 0x400>;
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "st,stm32-timers";
233 reg = <0x40001400 0x400>;
235 clock-names = "int";
239 compatible = "st,stm32-timer-trigger";
240 reg = <6>;
246 #address-cells = <1>;
247 #size-cells = <0>;
248 compatible = "st,stm32-timers";
249 reg = <0x40001800 0x400>;
251 clock-names = "int";
255 compatible = "st,stm32-pwm";
256 #pwm-cells = <3>;
261 compatible = "st,stm32-timer-trigger";
262 reg = <11>;
268 #address-cells = <1>;
269 #size-cells = <0>;
270 compatible = "st,stm32-timers";
271 reg = <0x40001C00 0x400>;
273 clock-names = "int";
277 compatible = "st,stm32-pwm";
278 #pwm-cells = <3>;
284 #address-cells = <1>;
285 #size-cells = <0>;
286 compatible = "st,stm32-timers";
287 reg = <0x40002000 0x400>;
289 clock-names = "int";
293 compatible = "st,stm32-pwm";
294 #pwm-cells = <3>;
300 compatible = "st,stm32-rtc";
301 reg = <0x40002800 0x400>;
303 assigned-clocks = <&rcc 1 CLK_RTC>;
304 assigned-clock-parents = <&rcc 1 CLK_LSE>;
305 interrupt-parent = <&exti>;
312 compatible = "st,stm32f7-uart";
313 reg = <0x40004400 0x400>;
320 compatible = "st,stm32f7-uart";
321 reg = <0x40004800 0x400>;
328 compatible = "st,stm32f7-uart";
329 reg = <0x40004c00 0x400>;
336 compatible = "st,stm32f7-uart";
337 reg = <0x40005000 0x400>;
344 compatible = "st,stm32f7-i2c";
345 reg = <0x40005400 0x400>;
350 #address-cells = <1>;
351 #size-cells = <0>;
356 compatible = "st,stm32f7-i2c";
357 reg = <0x40005800 0x400>;
362 #address-cells = <1>;
363 #size-cells = <0>;
368 compatible = "st,stm32f7-i2c";
369 reg = <0x40005C00 0x400>;
374 #address-cells = <1>;
375 #size-cells = <0>;
380 compatible = "st,stm32f7-i2c";
381 reg = <0x40006000 0x400>;
386 #address-cells = <1>;
387 #size-cells = <0>;
392 compatible = "st,stm32-cec";
393 reg = <0x40006C00 0x400>;
396 clock-names = "cec", "hdmi-cec";
401 compatible = "st,stm32f7-uart";
402 reg = <0x40007800 0x400>;
409 compatible = "st,stm32f7-uart";
410 reg = <0x40007c00 0x400>;
417 #address-cells = <1>;
418 #size-cells = <0>;
419 compatible = "st,stm32-timers";
420 reg = <0x40010000 0x400>;
422 clock-names = "int";
426 compatible = "st,stm32-pwm";
427 #pwm-cells = <3>;
432 compatible = "st,stm32-timer-trigger";
433 reg = <0>;
439 #address-cells = <1>;
440 #size-cells = <0>;
441 compatible = "st,stm32-timers";
442 reg = <0x40010400 0x400>;
444 clock-names = "int";
448 compatible = "st,stm32-pwm";
449 #pwm-cells = <3>;
454 compatible = "st,stm32-timer-trigger";
455 reg = <7>;
461 compatible = "st,stm32f7-uart";
462 reg = <0x40011000 0x400>;
469 compatible = "st,stm32f7-uart";
470 reg = <0x40011400 0x400>;
478 arm,primecell-periphid = <0x00880180>;
479 reg = <0x40011c00 0x400>;
481 clock-names = "apb_pclk";
483 max-frequency = <48000000>;
489 arm,primecell-periphid = <0x00880180>;
490 reg = <0x40012c00 0x400>;
492 clock-names = "apb_pclk";
494 max-frequency = <48000000>;
499 compatible = "st,stm32-syscfg", "syscon";
500 reg = <0x40013800 0x400>;
503 exti: interrupt-controller@40013c00 {
504 compatible = "st,stm32-exti";
505 interrupt-controller;
506 #interrupt-cells = <2>;
507 reg = <0x40013C00 0x400>;
512 #address-cells = <1>;
513 #size-cells = <0>;
514 compatible = "st,stm32-timers";
515 reg = <0x40014000 0x400>;
517 clock-names = "int";
521 compatible = "st,stm32-pwm";
522 #pwm-cells = <3>;
527 compatible = "st,stm32-timer-trigger";
528 reg = <8>;
534 #address-cells = <1>;
535 #size-cells = <0>;
536 compatible = "st,stm32-timers";
537 reg = <0x40014400 0x400>;
539 clock-names = "int";
543 compatible = "st,stm32-pwm";
544 #pwm-cells = <3>;
550 #address-cells = <1>;
551 #size-cells = <0>;
552 compatible = "st,stm32-timers";
553 reg = <0x40014800 0x400>;
555 clock-names = "int";
559 compatible = "st,stm32-pwm";
560 #pwm-cells = <3>;
565 pwrcfg: power-config@40007000 {
566 compatible = "st,stm32-power-config", "syscon";
567 reg = <0x40007000 0x400>;
571 compatible = "st,stm32f7-crc";
572 reg = <0x40023000 0x400>;
578 #reset-cells = <1>;
579 #clock-cells = <2>;
580 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
581 reg = <0x40023800 0x400>;
584 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
585 assigned-clock-rates = <1000000>;
588 dma1: dma-controller@40026000 {
589 compatible = "st,stm32-dma";
590 reg = <0x40026000 0x400>;
600 #dma-cells = <4>;
604 dma2: dma-controller@40026400 {
605 compatible = "st,stm32-dma";
606 reg = <0x40026400 0x400>;
616 #dma-cells = <4>;
622 compatible = "st,stm32f7-hsotg";
623 reg = <0x40040000 0x40000>;
626 clock-names = "otg";
627 g-rx-fifo-size = <256>;
628 g-np-tx-fifo-size = <32>;
629 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
634 compatible = "st,stm32f4x9-fsotg";
635 reg = <0x50000000 0x40000>;
638 clock-names = "otg";