Lines Matching +full:1 +full:c00

48 	#address-cells = <1>;
49 #size-cells = <1>;
87 #address-cells = <1>;
101 timer@1 {
103 reg = <1>;
117 #address-cells = <1>;
147 #address-cells = <1>;
168 timer5: timer@40000c00 {
175 timers5: timers@40000c00 {
176 #address-cells = <1>;
206 #address-cells = <1>;
230 #address-cells = <1>;
246 #address-cells = <1>;
267 timers13: timers@40001c00 {
268 #address-cells = <1>;
284 #address-cells = <1>;
302 clocks = <&rcc 1 CLK_RTC>;
303 assigned-clocks = <&rcc 1 CLK_RTC>;
304 assigned-clock-parents = <&rcc 1 CLK_LSE>;
306 interrupts = <17 1>;
315 clocks = <&rcc 1 CLK_USART2>;
323 clocks = <&rcc 1 CLK_USART3>;
327 usart4: serial@40004c00 {
331 clocks = <&rcc 1 CLK_UART4>;
339 clocks = <&rcc 1 CLK_UART5>;
349 clocks = <&rcc 1 CLK_I2C1>;
350 #address-cells = <1>;
361 clocks = <&rcc 1 CLK_I2C2>;
362 #address-cells = <1>;
367 i2c3: i2c@40005C00 {
373 clocks = <&rcc 1 CLK_I2C3>;
374 #address-cells = <1>;
385 clocks = <&rcc 1 CLK_I2C4>;
386 #address-cells = <1>;
391 cec: cec@40006c00 {
395 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
404 clocks = <&rcc 1 CLK_UART7>;
408 usart8: serial@40007c00 {
412 clocks = <&rcc 1 CLK_UART8>;
417 #address-cells = <1>;
439 #address-cells = <1>;
464 clocks = <&rcc 1 CLK_USART1>;
472 clocks = <&rcc 1 CLK_USART6>;
476 sdio2: sdio2@40011c00 {
487 sdio1: sdio1@40012c00 {
503 exti: interrupt-controller@40013c00 {
508 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
512 #address-cells = <1>;
534 #address-cells = <1>;
550 #address-cells = <1>;
578 #reset-cells = <1>;
584 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
645 clocks = <&rcc 1 0>;