boot/dts/stm32f746.dtsi

53 			#clock-cells = <0>;
55 			clock-frequency = <0>;
59 			#clock-cells = <0>;
65 			#clock-cells = <0>;
71 			#clock-cells = <0>;
80 			reg = <0x40000000 0x400>;
82 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
88 			#size-cells = <0>;
90 			reg = <0x40000000 0x400>;
91 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
110 			reg = <0x40000400 0x400>;
112 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
118 			#size-cells = <0>;
120 			reg = <0x40000400 0x400>;
121 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
140 			reg = <0x40000800 0x400>;
142 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
148 			#size-cells = <0>;
150 			reg = <0x40000800 0x400>;
151 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
170 			reg = <0x40000c00 0x400>;
172 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
177 			#size-cells = <0>;
179 			reg = <0x40000C00 0x400>;
180 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
199 			reg = <0x40001000 0x400>;
201 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
207 			#size-cells = <0>;
209 			reg = <0x40001000 0x400>;
210 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
223 			reg = <0x40001400 0x400>;
225 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
231 			#size-cells = <0>;
233 			reg = <0x40001400 0x400>;
234 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
247 			#size-cells = <0>;
249 			reg = <0x40001800 0x400>;
250 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
269 			#size-cells = <0>;
271 			reg = <0x40001C00 0x400>;
272 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
285 			#size-cells = <0>;
287 			reg = <0x40002000 0x400>;
288 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
301 			reg = <0x40002800 0x400>;
307 			st,syscfg = <&pwrcfg 0x00 0x100>;
313 			reg = <0x40004400 0x400>;
321 			reg = <0x40004800 0x400>;
329 			reg = <0x40004c00 0x400>;
337 			reg = <0x40005000 0x400>;
345 			reg = <0x40005400 0x400>;
351 			#size-cells = <0>;
357 			reg = <0x40005800 0x400>;
363 			#size-cells = <0>;
369 			reg = <0x40005C00 0x400>;
375 			#size-cells = <0>;
381 			reg = <0x40006000 0x400>;
387 			#size-cells = <0>;
393 			reg = <0x40006C00 0x400>;
395 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
402 			reg = <0x40007800 0x400>;
410 			reg = <0x40007c00 0x400>;
418 			#size-cells = <0>;
420 			reg = <0x40010000 0x400>;
421 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
431 			timer@0 {
433 				reg = <0>;
440 			#size-cells = <0>;
442 			reg = <0x40010400 0x400>;
443 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
462 			reg = <0x40011000 0x400>;
470 			reg = <0x40011400 0x400>;
478 			arm,primecell-periphid = <0x00880180>;
479 			reg = <0x40011c00 0x400>;
480 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
489 			arm,primecell-periphid = <0x00880180>;
490 			reg = <0x40012c00 0x400>;
491 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
500 			reg = <0x40013800 0x400>;
507 			reg = <0x40013C00 0x400>;
513 			#size-cells = <0>;
515 			reg = <0x40014000 0x400>;
516 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
535 			#size-cells = <0>;
537 			reg = <0x40014400 0x400>;
538 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
551 			#size-cells = <0>;
553 			reg = <0x40014800 0x400>;
554 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
567 			reg = <0x40007000 0x400>;
572 			reg = <0x40023000 0x400>;
573 			clocks = <&rcc 0 12>;
581 			reg = <0x40023800 0x400>;
590 			reg = <0x40026000 0x400>;
599 			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
606 			reg = <0x40026400 0x400>;
615 			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
623 			reg = <0x40040000 0x40000>;
625 			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
635 			reg = <0x50000000 0x40000>;
637 			clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
645 	clocks = <&rcc 1 0>;