Lines Matching full:rcc
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
100 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
109 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
130 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
160 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
169 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
190 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
198 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
219 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
228 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
243 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
252 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
268 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
290 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
306 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
320 clocks = <&rcc 1 CLK_RTC>;
321 assigned-clocks = <&rcc 1 CLK_RTC>;
322 assigned-clock-parents = <&rcc 1 CLK_LSE>;
343 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
353 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
361 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
369 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
380 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
388 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
397 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
398 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
409 resets = <&rcc STM32F4_APB1_RESET(I2C3)>;
410 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
419 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
420 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
445 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
453 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
462 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
484 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
505 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
516 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
524 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
536 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
548 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
560 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
573 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
586 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
596 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
618 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
640 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
656 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
673 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
686 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
699 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
700 clocks = <&rcc 1 CLK_LCD>;
708 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
712 rcc: rcc@40023810 { label
715 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
719 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
734 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
749 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
761 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
762 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
763 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
774 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
783 clocks = <&rcc 0 39>;
792 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
793 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
805 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
812 clocks = <&rcc 1 SYSTICK>;