Lines Matching +full:0 +full:x400
58 #clock-cells = <0>;
60 clock-frequency = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
78 clock-frequency = <0>;
85 reg = <0x1fff7800 0x400>;
89 reg = <0x22c 0x2>;
92 reg = <0x22e 0x2>;
98 reg = <0x40000000 0x400>;
100 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
106 #size-cells = <0>;
108 reg = <0x40000000 0x400>;
109 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
128 reg = <0x40000400 0x400>;
130 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
136 #size-cells = <0>;
138 reg = <0x40000400 0x400>;
139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
158 reg = <0x40000800 0x400>;
160 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
166 #size-cells = <0>;
168 reg = <0x40000800 0x400>;
169 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
188 reg = <0x40000c00 0x400>;
190 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
195 #size-cells = <0>;
197 reg = <0x40000C00 0x400>;
198 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
217 reg = <0x40001000 0x400>;
219 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
225 #size-cells = <0>;
227 reg = <0x40001000 0x400>;
228 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
241 reg = <0x40001400 0x400>;
243 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
249 #size-cells = <0>;
251 reg = <0x40001400 0x400>;
252 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
265 #size-cells = <0>;
267 reg = <0x40001800 0x400>;
268 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
287 #size-cells = <0>;
289 reg = <0x40001C00 0x400>;
290 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
303 #size-cells = <0>;
305 reg = <0x40002000 0x400>;
306 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
319 reg = <0x40002800 0x400>;
325 st,syscfg = <&pwrcfg 0x00 0x100>;
331 reg = <0x40003000 0x400>;
339 #size-cells = <0>;
341 reg = <0x40003800 0x400>;
343 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
349 #size-cells = <0>;
351 reg = <0x40003c00 0x400>;
353 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
359 reg = <0x40004400 0x400>;
361 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
367 reg = <0x40004800 0x400>;
369 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
371 dmas = <&dma1 1 4 0x400 0x0>,
372 <&dma1 3 4 0x400 0x0>;
378 reg = <0x40004c00 0x400>;
380 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
386 reg = <0x40005000 0x400>;
388 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
394 reg = <0x40005400 0x400>;
398 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
400 #size-cells = <0>;
406 reg = <0x40005c00 0x400>;
410 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
412 #size-cells = <0>;
418 reg = <0x40007400 0x400>;
420 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
423 #size-cells = <0>;
443 reg = <0x40007800 0x400>;
445 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
451 reg = <0x40007c00 0x400>;
453 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
459 #size-cells = <0>;
461 reg = <0x40010000 0x400>;
462 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
472 timer@0 {
474 reg = <0>;
481 #size-cells = <0>;
483 reg = <0x40010400 0x400>;
484 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
503 reg = <0x40011000 0x400>;
505 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
507 dmas = <&dma2 2 4 0x400 0x0>,
508 <&dma2 7 4 0x400 0x0>;
514 reg = <0x40011400 0x400>;
516 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
522 reg = <0x40012000 0x400>;
524 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
529 #size-cells = <0>;
532 adc1: adc@0 {
535 reg = <0x0>;
536 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
538 interrupts = <0>;
539 dmas = <&dma2 0 0 0x400 0x0>;
547 reg = <0x100>;
548 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
551 dmas = <&dma2 3 1 0x400 0x0>;
559 reg = <0x200>;
560 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
563 dmas = <&dma2 1 2 0x400 0x0>;
571 arm,primecell-periphid = <0x00880180>;
572 reg = <0x40012c00 0x400>;
573 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
582 #size-cells = <0>;
584 reg = <0x40013000 0x400>;
586 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
592 #size-cells = <0>;
594 reg = <0x40013400 0x400>;
596 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
602 reg = <0x40013800 0x400>;
609 reg = <0x40013C00 0x400>;
615 #size-cells = <0>;
617 reg = <0x40014000 0x400>;
618 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
637 #size-cells = <0>;
639 reg = <0x40014400 0x400>;
640 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
653 #size-cells = <0>;
655 reg = <0x40014800 0x400>;
656 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
669 #size-cells = <0>;
671 reg = <0x40015000 0x400>;
673 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
674 dmas = <&dma2 3 2 0x400 0x0>,
675 <&dma2 4 2 0x400 0x0>;
682 #size-cells = <0>;
684 reg = <0x40015400 0x400>;
686 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
692 reg = <0x40007000 0x400>;
697 reg = <0x40016800 0x200>;
707 reg = <0x40023000 0x400>;
708 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
716 reg = <0x40023800 0x400>;
725 reg = <0x40026000 0x400>;
734 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
740 reg = <0x40026400 0x400>;
749 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
756 reg = <0x40028000 0x8000>;
761 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
762 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
763 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
764 st,syscon = <&syscfg 0x4>;
772 reg = <0x40040000 0x40000>;
774 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
781 reg = <0x50000000 0x40000>;
783 clocks = <&rcc 0 39>;
790 reg = <0x50050000 0x400>;
793 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
796 pinctrl-0 = <&dcmi_pins>;
797 dmas = <&dma2 1 1 0x414 0x3>;
804 reg = <0x50060800 0x400>;
805 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;