boot/dts/spear1310.dtsi

1 // SPDX-License-Identifier: GPL-2.0-or-later
15 			compatible = "st,spear-spics-gpio";
17 			st-spics,peripcfg-reg = <0x3b0>;
18 			st-spics,sw-enable-bit = <12>;
19 			st-spics,cs-value-bit = <11>;
20 			st-spics,cs-enable-mask = <3>;
21 			st-spics,cs-enable-shift = <8>;
22 			gpio-controller;
23 			#gpio-cells = <2>;
27 			compatible = "st,spear1310-miphy";
30 			phy-id = <0>;
31 			#phy-cells = <1>;
36 			compatible = "st,spear1310-miphy";
39 			phy-id = <1>;
40 			#phy-cells = <1>;
45 			compatible = "st,spear1310-miphy";
48 			phy-id = <2>;
49 			#phy-cells = <1>;
54 			compatible = "snps,spear-ahci";
58 			phy-names = "sata-phy";
63 			compatible = "snps,spear-ahci";
67 			phy-names = "sata-phy";
72 			compatible = "snps,spear-ahci";
76 			phy-names = "sata-phy";
81 			compatible = "st,spear1340-pcie", "snps,dw-pcie";
83 			reg-names = "dbi", "config";
85 			interrupt-map-mask = <0 0 0 0>;
86 			interrupt-map = <0x0 0 &gic 0 68 0x4>;
87 			num-lanes = <1>;
89 			phy-names = "pcie-phy";
90 			#address-cells = <3>;
91 			#size-cells = <2>;
94 				0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
95 			bus-range = <0x00 0xff>;
100 			compatible = "st,spear1340-pcie", "snps,dw-pcie";
102 			reg-names = "dbi", "config";
104 			interrupt-map-mask = <0 0 0 0>;
105 			interrupt-map = <0x0 0 &gic 0 69 0x4>;
106 			num-lanes = <1>;
108 			phy-names = "pcie-phy";
109 			#address-cells = <3>;
110 			#size-cells = <2>;
113 				0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
114 			bus-range = <0x00 0xff>;
119 			compatible = "st,spear1340-pcie", "snps,dw-pcie";
121 			reg-names = "dbi", "config";
123 			interrupt-map-mask = <0 0 0 0>;
124 			interrupt-map = <0x0 0 &gic 0 70 0x4>;
125 			num-lanes = <1>;
127 			phy-names = "pcie-phy";
128 			#address-cells = <3>;
129 			#size-cells = <2>;
132 				0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
133 			bus-range = <0x00 0xff>;
138 			compatible = "st,spear600-gmac";
141 			interrupt-names = "macirq";
142 			phy-mode = "mii";
147 			compatible = "st,spear600-gmac";
150 			interrupt-names = "macirq";
151 			phy-mode = "mii";
156 			compatible = "st,spear600-gmac";
159 			interrupt-names = "macirq";
160 			phy-mode = "rmii";
165 			compatible = "st,spear600-gmac";
168 			interrupt-names = "macirq";
169 			phy-mode = "rgmii";
174 			compatible = "st,spear1310-pinmux";
176 			#gpio-range-cells = <3>;
181 				#address-cells = <1>;
182 				#size-cells = <0>;
183 				compatible = "snps,designware-i2c";
190 				#address-cells = <1>;
191 				#size-cells = <0>;
192 				compatible = "snps,designware-i2c";
199 				#address-cells = <1>;
200 				#size-cells = <0>;
201 				compatible = "snps,designware-i2c";
208 				#address-cells = <1>;
209 				#size-cells = <0>;
210 				compatible = "snps,designware-i2c";
217 				#address-cells = <1>;
218 				#size-cells = <0>;
219 				compatible = "snps,designware-i2c";
226 				#address-cells = <1>;
227 				#size-cells = <0>;
228 				compatible = "snps,designware-i2c";
235 				#address-cells = <1>;
236 				#size-cells = <0>;
237 				compatible = "snps,designware-i2c";
247 				#address-cells = <1>;
248 				#size-cells = <0>;
288 				st,thermal-flags = <0x7000>;
292 				compatible = "st,spear-plgpio";
295 				#interrupt-cells = <1>;
296 				interrupt-controller;
297 				gpio-controller;
298 				#gpio-cells = <2>;
299 				gpio-ranges = <&pinmux 0 0 246>;
302 				st-plgpio,ngpio = <246>;
303 				st-plgpio,enb-reg = <0xd0>;
304 				st-plgpio,wdata-reg = <0x90>;
305 				st-plgpio,dir-reg = <0xb0>;
306 				st-plgpio,ie-reg = <0x30>;
307 				st-plgpio,rdata-reg = <0x70>;
308 				st-plgpio,mis-reg = <0x10>;
309 				st-plgpio,eit-reg = <0x50>;