Lines Matching full:rst
6 #include <dt-bindings/reset/altr,rst-mgr.h>
87 resets = <&rst DMA_RESET>;
105 resets = <&rst CAN0_RESET>;
114 resets = <&rst CAN1_RESET>;
532 resets = <&rst LWHPS2FPGA_RESET>;
540 resets = <&rst HPS2FPGA_RESET>;
548 resets = <&rst FPGA2HPS_RESET>;
575 resets = <&rst EMAC0_RESET>;
593 resets = <&rst EMAC1_RESET>;
608 resets = <&rst GPIO0_RESET>;
629 resets = <&rst GPIO1_RESET>;
650 resets = <&rst GPIO2_RESET>;
670 resets = <&rst I2C0_RESET>;
681 resets = <&rst I2C1_RESET>;
692 resets = <&rst I2C2_RESET>;
703 resets = <&rst I2C3_RESET>;
761 resets = <&rst SDMMC_RESET>;
775 resets = <&rst NAND_RESET>;
795 resets = <&rst QSPI_RESET>;
799 rst: rstmgr@ffd05000 { label
801 compatible = "altr,rst-mgr";
814 resets = <&rst SDR_RESET>;
831 resets = <&rst SPIM0_RESET>;
844 resets = <&rst SPIM1_RESET>;
868 resets = <&rst SPTIMER0_RESET>;
878 resets = <&rst SPTIMER1_RESET>;
888 resets = <&rst OSC1TIMER0_RESET>;
898 resets = <&rst OSC1TIMER1_RESET>;
912 resets = <&rst UART0_RESET>;
925 resets = <&rst UART1_RESET>;
940 resets = <&rst USB0_RESET>;
953 resets = <&rst USB1_RESET>;
965 resets = <&rst L4WD0_RESET>;
974 resets = <&rst L4WD1_RESET>;