Lines Matching +full:reg +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC
8 #include <dt-bindings/clock/sh73a0-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-a9";
25 reg = <0>;
26 clock-frequency = <1196000000>;
28 power-domains = <&pd_a2sl>;
29 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
34 reg = <1>;
35 clock-frequency = <1196000000>;
37 power-domains = <&pd_a2sl>;
38 next-level-cache = <&L2>;
43 compatible = "arm,cortex-a9-global-timer";
44 reg = <0xf0000200 0x100>;
50 compatible = "arm,cortex-a9-twd-timer";
51 reg = <0xf0000600 0x20>;
56 gic: interrupt-controller@f0001000 {
57 compatible = "arm,cortex-a9-gic";
58 #interrupt-cells = <3>;
59 interrupt-controller;
60 reg = <0xf0001000 0x1000>,
64 L2: cache-controller@f0100000 {
65 compatible = "arm,pl310-cache";
66 reg = <0xf0100000 0x1000>;
68 power-domains = <&pd_a3sm>;
69 arm,data-latency = <3 3 3>;
70 arm,tag-latency = <2 2 2>;
71 arm,shared-override;
72 cache-unified;
73 cache-level = <2>;
76 sbsc2: memory-controller@fb400000 {
77 compatible = "renesas,sbsc-sh73a0";
78 reg = <0xfb400000 0x400>;
81 interrupt-names = "sec", "temp";
82 power-domains = <&pd_a4bc1>;
85 sbsc1: memory-controller@fe400000 {
86 compatible = "renesas,sbsc-sh73a0";
87 reg = <0xfe400000 0x400>;
90 interrupt-names = "sec", "temp";
91 power-domains = <&pd_a4bc0>;
95 compatible = "arm,cortex-a9-pmu";
98 interrupt-affinity = <&cpu0>, <&cpu1>;
102 compatible = "renesas,sh73a0-cmt1";
103 reg = <0xe6138000 0x200>;
106 clock-names = "fck";
107 power-domains = <&pd_c5>;
111 irqpin0: interrupt-controller@e6900000 {
112 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
113 #interrupt-cells = <2>;
114 interrupt-controller;
115 reg = <0xe6900000 4>,
129 power-domains = <&pd_a4s>;
130 control-parent;
133 irqpin1: interrupt-controller@e6900004 {
134 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
135 #interrupt-cells = <2>;
136 interrupt-controller;
137 reg = <0xe6900004 4>,
151 power-domains = <&pd_a4s>;
152 control-parent;
155 irqpin2: interrupt-controller@e6900008 {
156 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
157 #interrupt-cells = <2>;
158 interrupt-controller;
159 reg = <0xe6900008 4>,
173 power-domains = <&pd_a4s>;
174 control-parent;
177 irqpin3: interrupt-controller@e690000c {
178 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
179 #interrupt-cells = <2>;
180 interrupt-controller;
181 reg = <0xe690000c 4>,
195 power-domains = <&pd_a4s>;
196 control-parent;
200 #address-cells = <1>;
201 #size-cells = <0>;
202 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
203 reg = <0xe6820000 0x425>;
209 power-domains = <&pd_a3sp>;
214 #address-cells = <1>;
215 #size-cells = <0>;
216 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
217 reg = <0xe6822000 0x425>;
223 power-domains = <&pd_a3sp>;
228 #address-cells = <1>;
229 #size-cells = <0>;
230 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
231 reg = <0xe6824000 0x425>;
237 power-domains = <&pd_a3sp>;
242 #address-cells = <1>;
243 #size-cells = <0>;
244 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
245 reg = <0xe6826000 0x425>;
251 power-domains = <&pd_a3sp>;
256 #address-cells = <1>;
257 #size-cells = <0>;
258 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
259 reg = <0xe6828000 0x425>;
265 power-domains = <&pd_c5>;
270 compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif";
271 reg = <0xe6bd0000 0x100>;
275 power-domains = <&pd_a3sp>;
276 reg-io-width = <4>;
281 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
282 reg = <0xe6e20000 0x0064>;
285 power-domains = <&pd_a3sp>;
286 #address-cells = <1>;
287 #size-cells = <0>;
292 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
293 reg = <0xe6e10000 0x0064>;
296 power-domains = <&pd_a3sp>;
297 #address-cells = <1>;
298 #size-cells = <0>;
303 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
304 reg = <0xe6e00000 0x0064>;
307 power-domains = <&pd_a3sp>;
308 #address-cells = <1>;
309 #size-cells = <0>;
314 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
315 reg = <0xe6c90000 0x0064>;
318 power-domains = <&pd_a3sp>;
319 #address-cells = <1>;
320 #size-cells = <0>;
325 compatible = "renesas,sdhi-sh73a0";
326 reg = <0xee100000 0x100>;
331 power-domains = <&pd_a3sp>;
332 cap-sd-highspeed;
338 compatible = "renesas,sdhi-sh73a0";
339 reg = <0xee120000 0x100>;
343 power-domains = <&pd_a3sp>;
344 disable-wp;
345 cap-sd-highspeed;
350 compatible = "renesas,sdhi-sh73a0";
351 reg = <0xee140000 0x100>;
355 power-domains = <&pd_a3sp>;
356 disable-wp;
357 cap-sd-highspeed;
362 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
363 reg = <0xe6c40000 0x100>;
366 clock-names = "fck";
367 power-domains = <&pd_a3sp>;
372 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
373 reg = <0xe6c50000 0x100>;
376 clock-names = "fck";
377 power-domains = <&pd_a3sp>;
382 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
383 reg = <0xe6c60000 0x100>;
386 clock-names = "fck";
387 power-domains = <&pd_a3sp>;
392 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
393 reg = <0xe6c70000 0x100>;
396 clock-names = "fck";
397 power-domains = <&pd_a3sp>;
402 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
403 reg = <0xe6c80000 0x100>;
406 clock-names = "fck";
407 power-domains = <&pd_a3sp>;
412 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
413 reg = <0xe6cb0000 0x100>;
416 clock-names = "fck";
417 power-domains = <&pd_a3sp>;
422 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
423 reg = <0xe6cc0000 0x100>;
426 clock-names = "fck";
427 power-domains = <&pd_a3sp>;
432 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
433 reg = <0xe6cd0000 0x100>;
436 clock-names = "fck";
437 power-domains = <&pd_a3sp>;
442 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
443 reg = <0xe6c30000 0x100>;
446 clock-names = "fck";
447 power-domains = <&pd_a3sp>;
452 compatible = "renesas,pfc-sh73a0";
453 reg = <0xe6050000 0x8000>,
455 gpio-controller;
456 #gpio-cells = <2>;
457 gpio-ranges =
460 interrupts-extended =
469 power-domains = <&pd_c5>;
472 sysc: system-controller@e6180000 {
473 compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
474 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
476 pm-domains {
478 #address-cells = <1>;
479 #size-cells = <0>;
480 #power-domain-cells = <0>;
483 reg = <0>;
484 #power-domain-cells = <0>;
488 reg = <1>;
489 #power-domain-cells = <0>;
493 reg = <4>;
494 #power-domain-cells = <0>;
498 reg = <5>;
499 #power-domain-cells = <0>;
503 reg = <6>;
504 #power-domain-cells = <0>;
508 reg = <7>;
509 #power-domain-cells = <0>;
513 reg = <8>;
514 #address-cells = <1>;
515 #size-cells = <0>;
516 #power-domain-cells = <0>;
519 reg = <9>;
520 #power-domain-cells = <0>;
524 reg = <10>;
525 #power-domain-cells = <0>;
530 reg = <12>;
531 #address-cells = <1>;
532 #size-cells = <0>;
533 #power-domain-cells = <0>;
536 reg = <13>;
537 #address-cells = <1>;
538 #size-cells = <0>;
539 #power-domain-cells = <0>;
542 reg = <14>;
543 #address-cells = <1>;
544 #size-cells = <0>;
545 #power-domain-cells = <0>;
551 reg = <16>;
552 #address-cells = <1>;
553 #size-cells = <0>;
554 #power-domain-cells = <0>;
557 reg = <17>;
558 #power-domain-cells = <0>;
562 reg = <18>;
563 #power-domain-cells = <0>;
567 reg = <19>;
568 #address-cells = <1>;
569 #size-cells = <0>;
570 #power-domain-cells = <0>;
573 reg = <20>;
574 #power-domain-cells = <0>;
583 #sound-dai-cells = <1>;
584 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
585 reg = <0xec230000 0x400>;
588 power-domains = <&pd_a4mp>;
593 compatible = "renesas,bsc-sh73a0", "renesas,bsc",
594 "simple-pm-bus";
595 #address-cells = <1>;
596 #size-cells = <1>;
598 reg = <0xfec10000 0x400>;
601 power-domains = <&pd_a4s>;
605 #address-cells = <1>;
606 #size-cells = <1>;
611 compatible = "fixed-clock";
612 #clock-cells = <0>;
613 clock-frequency = <32768>;
616 compatible = "fixed-clock";
617 #clock-cells = <0>;
618 clock-frequency = <26000000>;
621 compatible = "fixed-clock";
622 #clock-cells = <0>;
624 clock-frequency = <0>;
627 compatible = "fixed-clock";
628 #clock-cells = <0>;
630 clock-frequency = <0>;
633 compatible = "fixed-clock";
634 #clock-cells = <0>;
636 clock-frequency = <0>;
639 compatible = "fixed-clock";
640 #clock-cells = <0>;
642 clock-frequency = <0>;
647 compatible = "renesas,sh73a0-cpg-clocks";
648 reg = <0xe6150000 0x10000>;
650 #clock-cells = <1>;
651 clock-output-names = "main", "pll0", "pll1", "pll2",
659 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
660 reg = <0xe6150008 4>;
665 #clock-cells = <0>;
668 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
669 reg = <0xe615000c 4>;
674 #clock-cells = <0>;
677 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
678 reg = <0xe615001c 4>;
683 #clock-cells = <0>;
686 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
687 reg = <0xe6150010 4>;
690 #clock-cells = <0>;
691 clock-output-names = "zb";
694 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
695 reg = <0xe6150014 4>;
698 #clock-cells = <0>;
701 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
702 reg = <0xe6150074 4>;
705 #clock-cells = <0>;
708 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
709 reg = <0xe6150078 4>;
712 #clock-cells = <0>;
715 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
716 reg = <0xe615007c 4>;
719 #clock-cells = <0>;
722 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
723 reg = <0xe6150018 4>;
726 #clock-cells = <0>;
729 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
730 reg = <0xe6150090 4>;
733 #clock-cells = <0>;
736 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
737 reg = <0xe6150080 4>;
740 #clock-cells = <0>;
743 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
744 reg = <0xe6150084 4>;
747 #clock-cells = <0>;
750 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
751 reg = <0xe6150094 4>;
754 #clock-cells = <0>;
757 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
758 reg = <0xe6150088 4>;
761 #clock-cells = <0>;
764 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
765 reg = <0xe615008c 4>;
768 #clock-cells = <0>;
771 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
772 reg = <0xe6150098 4>;
775 #clock-cells = <0>;
778 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
779 reg = <0xe615009c 4>;
782 #clock-cells = <0>;
785 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
786 reg = <0xe6150060 4>;
789 #clock-cells = <0>;
792 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
793 reg = <0xe6150064 4>;
797 #clock-cells = <0>;
802 compatible = "fixed-factor-clock";
804 #clock-cells = <0>;
805 clock-div = <2>;
806 clock-mult = <1>;
809 compatible = "fixed-factor-clock";
811 #clock-cells = <0>;
812 clock-div = <2>;
813 clock-mult = <1>;
816 compatible = "fixed-factor-clock";
818 #clock-cells = <0>;
819 clock-div = <7>;
820 clock-mult = <1>;
823 compatible = "fixed-factor-clock";
825 #clock-cells = <0>;
826 clock-div = <13>;
827 clock-mult = <1>;
830 compatible = "fixed-factor-clock";
832 #clock-cells = <0>;
833 clock-div = <4>;
834 clock-mult = <1>;
839 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
840 reg = <0xe6150130 4>, <0xe6150030 4>;
842 #clock-cells = <1>;
843 clock-indices = <
846 clock-output-names =
850 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
851 reg = <0xe6150134 4>, <0xe6150038 4>;
860 #clock-cells = <1>;
861 clock-indices = <
868 clock-output-names =
873 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
874 reg = <0xe6150138 4>, <0xe6150040 4>;
880 #clock-cells = <1>;
881 clock-indices = <
890 clock-output-names =
897 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
898 reg = <0xe615013c 4>, <0xe6150048 4>;
908 #clock-cells = <1>;
909 clock-indices = <
919 clock-output-names =
925 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
926 reg = <0xe6150140 4>, <0xe615004c 4>;
929 #clock-cells = <1>;
930 clock-indices = <
934 clock-output-names =
938 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
939 reg = <0xe6150144 4>, <0xe615003c 4>;
941 #clock-cells = <1>;
942 clock-indices = <
945 clock-output-names =