Lines Matching +full:pwm +full:- +full:names
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/rv1108-cru.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 interrupt-parent = <&gic>;
28 #address-cells = <1>;
29 #size-cells = <0>;
33 compatible = "arm,cortex-a7";
35 clock-latency = <40000>;
37 #cooling-cells = <2>; /* min followed by max */
38 dynamic-power-coefficient = <75>;
39 operating-points-v2 = <&cpu_opp_table>;
44 compatible = "operating-points-v2";
46 opp-408000000 {
47 opp-hz = /bits/ 64 <408000000>;
48 opp-microvolt = <975000>;
49 clock-latency-ns = <40000>;
51 opp-600000000 {
52 opp-hz = /bits/ 64 <600000000>;
53 opp-microvolt = <975000>;
54 clock-latency-ns = <40000>;
56 opp-816000000 {
57 opp-hz = /bits/ 64 <816000000>;
58 opp-microvolt = <1025000>;
59 clock-latency-ns = <40000>;
61 opp-1008000000 {
62 opp-hz = /bits/ 64 <1008000000>;
63 opp-microvolt = <1150000>;
64 clock-latency-ns = <40000>;
68 arm-pmu {
69 compatible = "arm,cortex-a7-pmu";
74 compatible = "arm,armv7-timer";
77 arm,cpu-registers-not-fw-configured;
78 clock-frequency = <24000000>;
82 compatible = "fixed-clock";
83 clock-frequency = <24000000>;
84 clock-output-names = "xin24m";
85 #clock-cells = <0>;
89 compatible = "simple-bus";
90 #address-cells = <1>;
91 #size-cells = <1>;
98 #dma-cells = <1>;
99 arm,pl330-broken-no-flushp;
100 arm,pl330-periph-burst;
102 clock-names = "apb_pclk";
107 compatible = "mmio-sram";
109 #address-cells = <1>;
110 #size-cells = <1>;
115 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
118 reg-shift = <2>;
119 reg-io-width = <4>;
120 clock-frequency = <24000000>;
122 clock-names = "baudclk", "apb_pclk";
124 pinctrl-names = "default";
125 pinctrl-0 = <&uart2m0_xfer>;
130 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
133 reg-shift = <2>;
134 reg-io-width = <4>;
135 clock-frequency = <24000000>;
137 clock-names = "baudclk", "apb_pclk";
139 pinctrl-names = "default";
140 pinctrl-0 = <&uart1_xfer>;
145 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
148 reg-shift = <2>;
149 reg-io-width = <4>;
150 clock-frequency = <24000000>;
152 clock-names = "baudclk", "apb_pclk";
154 pinctrl-names = "default";
155 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
160 compatible = "rockchip,rv1108-i2c";
163 #address-cells = <1>;
164 #size-cells = <0>;
166 clock-names = "i2c", "pclk";
167 pinctrl-names = "default";
168 pinctrl-0 = <&i2c1_xfer>;
174 compatible = "rockchip,rv1108-i2c";
177 #address-cells = <1>;
178 #size-cells = <0>;
180 clock-names = "i2c", "pclk";
181 pinctrl-names = "default";
182 pinctrl-0 = <&i2c2m1_xfer>;
188 compatible = "rockchip,rv1108-i2c";
191 #address-cells = <1>;
192 #size-cells = <0>;
194 clock-names = "i2c", "pclk";
195 pinctrl-names = "default";
196 pinctrl-0 = <&i2c3_xfer>;
202 compatible = "rockchip,rv1108-spi";
206 clock-names = "spiclk", "apb_pclk";
208 dma-names = "tx", "rx";
209 #address-cells = <1>;
210 #size-cells = <0>;
214 pwm4: pwm@10280000 {
215 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
219 clock-names = "pwm", "pclk";
220 pinctrl-names = "default";
221 pinctrl-0 = <&pwm4_pin>;
222 #pwm-cells = <3>;
226 pwm5: pwm@10280010 {
227 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
231 clock-names = "pwm", "pclk";
232 pinctrl-names = "default";
233 pinctrl-0 = <&pwm5_pin>;
234 #pwm-cells = <3>;
238 pwm6: pwm@10280020 {
239 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
243 clock-names = "pwm", "pclk";
244 pinctrl-names = "default";
245 pinctrl-0 = <&pwm6_pin>;
246 #pwm-cells = <3>;
250 pwm7: pwm@10280030 {
251 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
255 clock-names = "pwm", "pclk";
256 pinctrl-names = "default";
257 pinctrl-0 = <&pwm7_pin>;
258 #pwm-cells = <3>;
263 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
265 #address-cells = <1>;
266 #size-cells = <1>;
268 u2phy: usb2-phy@100 {
269 compatible = "rockchip,rv1108-usb2phy";
272 clock-names = "phyclk";
273 #clock-cells = <0>;
274 clock-output-names = "usbphy";
278 u2phy_otg: otg-port {
280 interrupt-names = "otg-mux";
281 #phy-cells = <0>;
285 u2phy_host: host-port {
287 interrupt-names = "linestate";
288 #phy-cells = <0>;
295 compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
299 clock-names = "timer", "pclk";
303 compatible = "snps,dw-wdt";
307 clock-names = "pclk_wdt";
311 thermal-zones {
312 soc_thermal: soc-thermal {
313 polling-delay-passive = <20>;
314 polling-delay = <1000>;
315 sustainable-power = <50>;
316 thermal-sensors = <&tsadc 0>;
319 threshold: trip-point0 {
324 target: trip-point1 {
329 soc_crit: soc-crit {
336 cooling-maps {
339 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
347 compatible = "rockchip,rv1108-tsadc";
350 assigned-clocks = <&cru SCLK_TSADC>;
351 assigned-clock-rates = <750000>;
353 clock-names = "tsadc", "apb_pclk";
354 pinctrl-names = "init", "default", "sleep";
355 pinctrl-0 = <&otp_pin>;
356 pinctrl-1 = <&otp_out>;
357 pinctrl-2 = <&otp_pin>;
359 reset-names = "tsadc-apb";
360 rockchip,hw-tshut-temp = <120000>;
361 #thermal-sensor-cells = <1>;
366 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
369 #io-channel-cells = <1>;
371 clock-names = "saradc", "apb_pclk";
376 compatible = "rockchip,rv1108-i2c";
379 #address-cells = <1>;
380 #size-cells = <0>;
382 clock-names = "i2c", "pclk";
383 pinctrl-names = "default";
384 pinctrl-0 = <&i2c0_xfer>;
389 pwm0: pwm@20040000 {
390 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
394 clock-names = "pwm", "pclk";
395 pinctrl-names = "default";
396 pinctrl-0 = <&pwm0_pin>;
397 #pwm-cells = <3>;
401 pwm1: pwm@20040010 {
402 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
406 clock-names = "pwm", "pclk";
407 pinctrl-names = "default";
408 pinctrl-0 = <&pwm1_pin>;
409 #pwm-cells = <3>;
413 pwm2: pwm@20040020 {
414 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
418 clock-names = "pwm", "pclk";
419 pinctrl-names = "default";
420 pinctrl-0 = <&pwm2_pin>;
421 #pwm-cells = <3>;
425 pwm3: pwm@20040030 {
426 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
430 clock-names = "pwm", "pclk";
431 pinctrl-names = "default";
432 pinctrl-0 = <&pwm3_pin>;
433 #pwm-cells = <3>;
438 compatible = "rockchip,rv1108-pmugrf", "syscon";
443 compatible = "rockchip,rv1108-usbgrf", "syscon";
447 cru: clock-controller@20200000 {
448 compatible = "rockchip,rv1108-cru";
451 #clock-cells = <1>;
452 #reset-cells = <1>;
456 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
461 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
462 fifo-depth = <0x100>;
463 max-frequency = <150000000>;
468 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
473 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
474 fifo-depth = <0x100>;
475 max-frequency = <150000000>;
480 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
485 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
486 fifo-depth = <0x100>;
487 max-frequency = <100000000>;
488 pinctrl-names = "default";
489 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
494 compatible = "generic-ehci";
499 phy-names = "usb";
504 compatible = "generic-ohci";
509 phy-names = "usb";
514 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
519 clock-names = "otg";
521 g-np-tx-fifo-size = <16>;
522 g-rx-fifo-size = <280>;
523 g-tx-fifo-size = <256 128 128 64 32 16>;
525 phy-names = "usb2-phy";
530 compatible = "rockchip,rv1108-gmac";
534 interrupt-names = "macirq", "eth_wake_irq";
539 clock-names = "stmmaceth",
544 phy-mode = "rmii";
545 pinctrl-names = "default";
546 pinctrl-0 = <&rmii_pins>;
551 gic: interrupt-controller@32010000 {
552 compatible = "arm,gic-400";
553 interrupt-controller;
554 #interrupt-cells = <3>;
555 #address-cells = <0>;
565 compatible = "rockchip,rv1108-pinctrl";
568 #address-cells = <1>;
569 #size-cells = <1>;
573 compatible = "rockchip,gpio-bank";
578 gpio-controller;
579 #gpio-cells = <2>;
581 interrupt-controller;
582 #interrupt-cells = <2>;
586 compatible = "rockchip,gpio-bank";
591 gpio-controller;
592 #gpio-cells = <2>;
594 interrupt-controller;
595 #interrupt-cells = <2>;
599 compatible = "rockchip,gpio-bank";
604 gpio-controller;
605 #gpio-cells = <2>;
607 interrupt-controller;
608 #interrupt-cells = <2>;
612 compatible = "rockchip,gpio-bank";
617 gpio-controller;
618 #gpio-cells = <2>;
620 interrupt-controller;
621 #interrupt-cells = <2>;
624 pcfg_pull_up: pcfg-pull-up {
625 bias-pull-up;
628 pcfg_pull_down: pcfg-pull-down {
629 bias-pull-down;
632 pcfg_pull_none: pcfg-pull-none {
633 bias-disable;
636 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
637 drive-strength = <8>;
640 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
641 drive-strength = <12>;
644 pcfg_pull_none_smt: pcfg-pull-none-smt {
645 bias-disable;
646 input-schmitt-enable;
649 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
650 bias-pull-up;
651 drive-strength = <8>;
654 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
655 drive-strength = <4>;
658 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
659 bias-pull-up;
660 drive-strength = <4>;
663 pcfg_output_high: pcfg-output-high {
664 output-high;
667 pcfg_output_low: pcfg-output-low {
668 output-low;
671 pcfg_input_high: pcfg-input-high {
672 bias-pull-up;
673 input-enable;
677 emmc_bus8: emmc-bus8 {
688 emmc_clk: emmc-clk {
692 emmc_cmd: emmc-cmd {
698 rmii_pins: rmii-pins {
713 i2c0_xfer: i2c0-xfer {
720 i2c1_xfer: i2c1-xfer {
727 i2c2m1_xfer: i2c2m1-xfer {
732 i2c2m1_pins: i2c2m1-pins {
739 i2c2m05v_xfer: i2c2m05v-xfer {
744 i2c2m05v_pins: i2c2m05v-pins {
751 i2c3_xfer: i2c3-xfer {
758 pwm0_pin: pwm0-pin {
764 pwm1_pin: pwm1-pin {
770 pwm2_pin: pwm2-pin {
776 pwm3_pin: pwm3-pin {
782 pwm4_pin: pwm4-pin {
788 pwm5_pin: pwm5-pin {
794 pwm6_pin: pwm6-pin {
800 pwm7_pin: pwm7-pin {
806 sdmmc_clk: sdmmc-clk {
810 sdmmc_cmd: sdmmc-cmd {
814 sdmmc_cd: sdmmc-cd {
818 sdmmc_bus1: sdmmc-bus1 {
822 sdmmc_bus4: sdmmc-bus4 {
831 spim0_clk: spim0-clk {
835 spim0_cs0: spim0-cs0 {
839 spim0_tx: spim0-tx {
843 spim0_rx: spim0-rx {
849 spim1_clk: spim1-clk {
853 spim1_cs0: spim1-cs0 {
857 spim1_rx: spim1-rx {
861 spim1_tx: spim1-tx {
867 otp_out: otp-out {
871 otp_pin: otp-pin {
877 uart0_xfer: uart0-xfer {
882 uart0_cts: uart0-cts {
886 uart0_rts: uart0-rts {
890 uart0_rts_pin: uart0-rts-pin {
896 uart1_xfer: uart1-xfer {
901 uart1_cts: uart1-cts {
905 uart1_rts: uart1-rts {
911 uart2m0_xfer: uart2m0-xfer {
918 uart2m1_xfer: uart2m1-xfer {
925 uart2_5v_cts: uart2_5v-cts {
929 uart2_5v_rts: uart2_5v-rts {