boot/dts/rk3xxx.dtsi

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 	#address-cells = <1>;
13 	#size-cells = <1>;
15 	interrupt-parent = <&gic>;
36 		compatible = "simple-bus";
37 		#address-cells = <1>;
38 		#size-cells = <1>;
41 		dmac1_s: dma-controller@20018000 {
46 			#dma-cells = <1>;
47 			arm,pl330-broken-no-flushp;
48 			arm,pl330-periph-burst;
50 			clock-names = "apb_pclk";
53 		dmac1_ns: dma-controller@2001c000 {
58 			#dma-cells = <1>;
59 			arm,pl330-broken-no-flushp;
60 			arm,pl330-periph-burst;
62 			clock-names = "apb_pclk";
66 		dmac2: dma-controller@20078000 {
71 			#dma-cells = <1>;
72 			arm,pl330-broken-no-flushp;
73 			arm,pl330-periph-burst;
75 			clock-names = "apb_pclk";
80 		compatible = "fixed-clock";
81 		clock-frequency = <24000000>;
82 		#clock-cells = <0>;
83 		clock-output-names = "xin24m";
87 		compatible = "arm,mali-400";
90 		clock-names = "bus", "core";
91 		assigned-clocks = <&cru ACLK_GPU>;
92 		assigned-clock-rates = <100000000>;
97 	L2: cache-controller@10138000 {
98 		compatible = "arm,pl310-cache";
100 		cache-unified;
101 		cache-level = <2>;
105 		compatible = "arm,cortex-a9-scu";
109 	global_timer: global-timer@1013c200 {
110 		compatible = "arm,cortex-a9-global-timer";
116 	local_timer: local-timer@1013c600 {
117 		compatible = "arm,cortex-a9-twd-timer";
123 	gic: interrupt-controller@1013d000 {
124 		compatible = "arm,cortex-a9-gic";
125 		interrupt-controller;
126 		#interrupt-cells = <3>;
132 		compatible = "snps,dw-apb-uart";
135 		reg-shift = <2>;
136 		reg-io-width = <1>;
137 		clock-names = "baudclk", "apb_pclk";
143 		compatible = "snps,dw-apb-uart";
146 		reg-shift = <2>;
147 		reg-io-width = <1>;
148 		clock-names = "baudclk", "apb_pclk";
154 		compatible = "syscon";
159 		compatible = "syscon";
164 		compatible = "syscon";
169 		compatible = "syscon";
174 		compatible = "syscon";
179 		compatible = "syscon";
184 		compatible = "syscon";
189 		compatible = "syscon";
194 		compatible = "rockchip,rk3066-usb", "snps,dwc2";
198 		clock-names = "otg";
200 		g-np-tx-fifo-size = <16>;
201 		g-rx-fifo-size = <275>;
202 		g-tx-fifo-size = <256 128 128 64 64 32>;
204 		phy-names = "usb2-phy";
213 		clock-names = "otg";
216 		phy-names = "usb2-phy";
221 		compatible = "snps,arc-emac";
224 		#address-cells = <1>;
225 		#size-cells = <0>;
230 		clock-names = "hclk", "macref";
231 		max-speed = <100>;
232 		phy-mode = "rmii";
238 		compatible = "rockchip,rk2928-dw-mshc";
242 		clock-names = "biu", "ciu";
244 		dma-names = "rx-tx";
245 		fifo-depth = <256>;
247 		reset-names = "reset";
252 		compatible = "rockchip,rk2928-dw-mshc";
256 		clock-names = "biu", "ciu";
258 		dma-names = "rx-tx";
259 		fifo-depth = <256>;
261 		reset-names = "reset";
266 		compatible = "rockchip,rk2928-dw-mshc";
270 		clock-names = "biu", "ciu";
272 		dma-names = "rx-tx";
273 		fifo-depth = <256>;
275 		reset-names = "reset";
280 		compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
283 		reboot-mode {
284 			compatible = "syscon-reboot-mode";
286 			mode-normal = <BOOT_NORMAL>;
287 			mode-recovery = <BOOT_RECOVERY>;
288 			mode-bootloader = <BOOT_FASTBOOT>;
289 			mode-loader = <BOOT_BL_DOWNLOAD>;
294 		compatible = "syscon";
299 		compatible = "rockchip,rk3066-i2c";
302 		#address-cells = <1>;
303 		#size-cells = <0>;
307 		clock-names = "i2c";
314 		compatible = "rockchip,rk3066-i2c";
317 		#address-cells = <1>;
318 		#size-cells = <0>;
323 		clock-names = "i2c";
329 		compatible = "rockchip,rk2928-pwm";
331 		#pwm-cells = <2>;
337 		compatible = "rockchip,rk2928-pwm";
339 		#pwm-cells = <2>;
345 		compatible = "snps,dw-wdt";
353 		compatible = "rockchip,rk2928-pwm";
355 		#pwm-cells = <2>;
361 		compatible = "rockchip,rk2928-pwm";
363 		#pwm-cells = <2>;
369 		compatible = "rockchip,rk3066-i2c";
372 		#address-cells = <1>;
373 		#size-cells = <0>;
378 		clock-names = "i2c";
384 		compatible = "rockchip,rk3066-i2c";
387 		#address-cells = <1>;
388 		#size-cells = <0>;
393 		clock-names = "i2c";
399 		compatible = "rockchip,rk3066-i2c";
402 		#address-cells = <1>;
403 		#size-cells = <0>;
408 		clock-names = "i2c";
414 		compatible = "snps,dw-apb-uart";
417 		reg-shift = <2>;
418 		reg-io-width = <1>;
419 		clock-names = "baudclk", "apb_pclk";
425 		compatible = "snps,dw-apb-uart";
428 		reg-shift = <2>;
429 		reg-io-width = <1>;
430 		clock-names = "baudclk", "apb_pclk";
439 		#io-channel-cells = <1>;
441 		clock-names = "saradc", "apb_pclk";
443 		reset-names = "saradc-apb";
448 		compatible = "rockchip,rk3066-spi";
450 		clock-names = "spiclk", "apb_pclk";
453 		#address-cells = <1>;
454 		#size-cells = <0>;
456 		dma-names = "tx", "rx";
461 		compatible = "rockchip,rk3066-spi";
463 		clock-names = "spiclk", "apb_pclk";
466 		#address-cells = <1>;
467 		#size-cells = <0>;
469 		dma-names = "tx", "rx";