boot/dts/r8a7779.dtsi

1 // SPDX-License-Identifier: GPL-2.0
3  * Device Tree Source for the R-Car H1 (R8A77790) SoC
9 #include <dt-bindings/clock/r8a7779-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a7779-sysc.h>
16 	interrupt-parent = <&gic>;
17 	#address-cells = <1>;
18 	#size-cells = <1>;
21 		#address-cells = <1>;
22 		#size-cells = <0>;
26 			compatible = "arm,cortex-a9";
27 			reg = <0>;
28 			clock-frequency = <1000000000>;
33 			compatible = "arm,cortex-a9";
34 			reg = <1>;
35 			clock-frequency = <1000000000>;
37 			power-domains = <&sysc R8A7779_PD_ARM1>;
41 			compatible = "arm,cortex-a9";
42 			reg = <2>;
43 			clock-frequency = <1000000000>;
45 			power-domains = <&sysc R8A7779_PD_ARM2>;
49 			compatible = "arm,cortex-a9";
50 			reg = <3>;
51 			clock-frequency = <1000000000>;
53 			power-domains = <&sysc R8A7779_PD_ARM3>;
63 	gic: interrupt-controller@f0001000 {
64 		compatible = "arm,cortex-a9-gic";
65 		#interrupt-cells = <3>;
66 		interrupt-controller;
67 		reg = <0xf0001000 0x1000>,
72 		compatible = "arm,cortex-a9-global-timer";
73 		reg = <0xf0000200 0x100>;
80 		compatible = "arm,cortex-a9-twd-timer";
81 		reg = <0xf0000600 0x20>;
88 		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
89 		reg = <0xffc40000 0x2c>;
91 		#gpio-cells = <2>;
92 		gpio-controller;
93 		gpio-ranges = <&pfc 0 0 32>;
94 		#interrupt-cells = <2>;
95 		interrupt-controller;
99 		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
100 		reg = <0xffc41000 0x2c>;
102 		#gpio-cells = <2>;
103 		gpio-controller;
104 		gpio-ranges = <&pfc 0 32 32>;
105 		#interrupt-cells = <2>;
106 		interrupt-controller;
110 		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
111 		reg = <0xffc42000 0x2c>;
113 		#gpio-cells = <2>;
114 		gpio-controller;
115 		gpio-ranges = <&pfc 0 64 32>;
116 		#interrupt-cells = <2>;
117 		interrupt-controller;
121 		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
122 		reg = <0xffc43000 0x2c>;
124 		#gpio-cells = <2>;
125 		gpio-controller;
126 		gpio-ranges = <&pfc 0 96 32>;
127 		#interrupt-cells = <2>;
128 		interrupt-controller;
132 		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
133 		reg = <0xffc44000 0x2c>;
135 		#gpio-cells = <2>;
136 		gpio-controller;
137 		gpio-ranges = <&pfc 0 128 32>;
138 		#interrupt-cells = <2>;
139 		interrupt-controller;
143 		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
144 		reg = <0xffc45000 0x2c>;
146 		#gpio-cells = <2>;
147 		gpio-controller;
148 		gpio-ranges = <&pfc 0 160 32>;
149 		#interrupt-cells = <2>;
150 		interrupt-controller;
154 		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
155 		reg = <0xffc46000 0x2c>;
157 		#gpio-cells = <2>;
158 		gpio-controller;
159 		gpio-ranges = <&pfc 0 192 9>;
160 		#interrupt-cells = <2>;
161 		interrupt-controller;
164 	irqpin0: interrupt-controller@fe78001c {
165 		compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
166 		#interrupt-cells = <2>;
168 		interrupt-controller;
169 		reg = <0xfe78001c 4>,
179 		sense-bitfield-width = <2>;
183 		#address-cells = <1>;
184 		#size-cells = <0>;
185 		compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
186 		reg = <0xffc70000 0x1000>;
189 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
194 		#address-cells = <1>;
195 		#size-cells = <0>;
196 		compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
197 		reg = <0xffc71000 0x1000>;
200 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
205 		#address-cells = <1>;
206 		#size-cells = <0>;
207 		compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
208 		reg = <0xffc72000 0x1000>;
211 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
216 		#address-cells = <1>;
217 		#size-cells = <0>;
218 		compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
219 		reg = <0xffc73000 0x1000>;
222 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
227 		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
229 		reg = <0xffe40000 0x100>;
233 		clock-names = "fck", "brg_int", "scif_clk";
234 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
239 		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
241 		reg = <0xffe41000 0x100>;
245 		clock-names = "fck", "brg_int", "scif_clk";
246 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
251 		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
253 		reg = <0xffe42000 0x100>;
257 		clock-names = "fck", "brg_int", "scif_clk";
258 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
263 		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
265 		reg = <0xffe43000 0x100>;
269 		clock-names = "fck", "brg_int", "scif_clk";
270 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
275 		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
277 		reg = <0xffe44000 0x100>;
281 		clock-names = "fck", "brg_int", "scif_clk";
282 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
287 		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
289 		reg = <0xffe45000 0x100>;
293 		clock-names = "fck", "brg_int", "scif_clk";
294 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
299 		compatible = "renesas,hscif-r8a7779",
300 			     "renesas,rcar-gen1-hscif", "renesas,hscif";
301 		reg = <0xffe48000 96>;
306 		clock-names = "fck", "brg_int", "scif_clk";
307 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
312 		compatible = "renesas,hscif-r8a7779",
313 			     "renesas,rcar-gen1-hscif", "renesas,hscif";
314 		reg = <0xffe49000 96>;
319 		clock-names = "fck", "brg_int", "scif_clk";
320 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
325 		compatible = "renesas,pfc-r8a7779";
326 		reg = <0xfffc0000 0x23c>;
330 		compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
331 		reg = <0xffc48000 0x38>;
335 		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
336 		reg = <0xffd80000 0x30>;
341 		clock-names = "fck";
342 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
350 		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
351 		reg = <0xffd81000 0x30>;
356 		clock-names = "fck";
357 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
365 		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
366 		reg = <0xffd82000 0x30>;
371 		clock-names = "fck";
372 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
380 		compatible = "renesas,sata-r8a7779";
381 		reg = <0xfc600000 0x200000>;
384 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
389 		compatible = "renesas,sdhi-r8a7779",
390 			     "renesas,rcar-gen1-sdhi";
391 		reg = <0xffe4c000 0x100>;
394 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
399 		compatible = "renesas,sdhi-r8a7779",
400 			     "renesas,rcar-gen1-sdhi";
401 		reg = <0xffe4d000 0x100>;
404 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
409 		compatible = "renesas,sdhi-r8a7779",
410 			     "renesas,rcar-gen1-sdhi";
411 		reg = <0xffe4e000 0x100>;
414 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
419 		compatible = "renesas,sdhi-r8a7779",
420 			     "renesas,rcar-gen1-sdhi";
421 		reg = <0xffe4f000 0x100>;
424 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
429 		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
430 		reg = <0xfffc7000 0x18>;
432 		#address-cells = <1>;
433 		#size-cells = <0>;
435 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
440 		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
441 		reg = <0xfffc8000 0x18>;
443 		#address-cells = <1>;
444 		#size-cells = <0>;
446 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
451 		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
452 		reg = <0xfffc6000 0x18>;
454 		#address-cells = <1>;
455 		#size-cells = <0>;
457 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
462 		compatible = "renesas,du-r8a7779";
463 		reg = <0xfff80000 0x40000>;
466 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
470 			#address-cells = <1>;
471 			#size-cells = <0>;
474 				reg = <0>;
479 				reg = <1>;
487 		#address-cells = <1>;
488 		#size-cells = <1>;
493 			compatible = "fixed-clock";
494 			#clock-cells = <0>;
496 			clock-frequency = <0>;
501 			compatible = "fixed-clock";
502 			#clock-cells = <0>;
504 			clock-frequency = <0>;
509 			compatible = "renesas,r8a7779-cpg-clocks";
510 			reg = <0xffc80000 0x30>;
512 			#clock-cells = <1>;
513 			clock-output-names = "plla", "z", "zs", "s",
515 			#power-domain-cells = <0>;
520 			compatible = "fixed-factor-clock";
522 			#clock-cells = <0>;
523 			clock-div = <2>;
524 			clock-mult = <1>;
527 			compatible = "fixed-factor-clock";
529 			#clock-cells = <0>;
530 			clock-div = <8>;
531 			clock-mult = <1>;
534 			compatible = "fixed-factor-clock";
536 			#clock-cells = <0>;
537 			clock-div = <16>;
538 			clock-mult = <1>;
541 			compatible = "fixed-factor-clock";
543 			#clock-cells = <0>;
544 			clock-div = <24>;
545 			clock-mult = <1>;
550 			compatible = "renesas,r8a7779-mstp-clocks",
551 				     "renesas,cpg-mstp-clocks";
552 			reg = <0xffc80030 4>;
569 			#clock-cells = <1>;
570 			clock-indices = <
580 			clock-output-names =
587 			compatible = "renesas,r8a7779-mstp-clocks",
588 				     "renesas,cpg-mstp-clocks";
589 			reg = <0xffc80034 4>, <0xffc80044 4>;
600 			#clock-cells = <1>;
601 			clock-indices = <
608 			clock-output-names =
616 			compatible = "renesas,r8a7779-mstp-clocks",
617 				     "renesas,cpg-mstp-clocks";
618 			reg = <0xffc8003c 4>;
621 			#clock-cells = <1>;
622 			clock-indices = <
627 			clock-output-names =
635 		reg = <0xff000044 4>;
638 	rst: reset-controller@ffcc0000 {
639 		compatible = "renesas,r8a7779-reset-wdt";
640 		reg = <0xffcc0000 0x48>;
643 	sysc: system-controller@ffd85000 {
644 		compatible = "renesas,r8a7779-sysc";
645 		reg = <0xffd85000 0x0200>;
646 		#power-domain-cells = <1>;