boot/dts/r8a73a4.dtsi

1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/r8a73a4-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
15 	interrupt-parent = <&gic>;
16 	#address-cells = <2>;
17 	#size-cells = <2>;
20 		#address-cells = <1>;
21 		#size-cells = <0>;
25 			compatible = "arm,cortex-a15";
27 			clocks = <&cpg_clocks R8A73A4_CLK_Z>;
28 			clock-frequency = <1500000000>;
29 			power-domains = <&pd_a2sl>;
30 			next-level-cache = <&L2_CA15>;
33 		L2_CA15: cache-controller-0 {
35 			clocks = <&cpg_clocks R8A73A4_CLK_Z>;
36 			power-domains = <&pd_a3sm>;
37 			cache-unified;
38 			cache-level = <2>;
41 		L2_CA7: cache-controller-1 {
43 			clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
44 			power-domains = <&pd_a3km>;
45 			cache-unified;
46 			cache-level = <2>;
51 		compatible = "arm,coresight-etm3x";
52 		power-domains = <&pd_d4>;
56 		compatible = "arm,armv7-timer";
63 	dbsc1: memory-controller@e6790000 {
64 		compatible = "renesas,dbsc-r8a73a4";
66 		power-domains = <&pd_a3bc>;
69 	dbsc2: memory-controller@e67a0000 {
70 		compatible = "renesas,dbsc-r8a73a4";
72 		power-domains = <&pd_a3bc>;
75 	dmac: dma-multiplexer {
76 		compatible = "renesas,shdma-mux";
77 		#dma-cells = <1>;
78 		dma-channels = <20>;
79 		dma-requests = <256>;
80 		#address-cells = <2>;
81 		#size-cells = <2>;
84 		dma0: dma-controller@e6700020 {
85 			compatible = "renesas,shdma-r8a73a4";
108 			interrupt-names = "error",
114 			clocks = <&mstp2_clks R8A73A4_CLK_DMAC>;
115 			power-domains = <&pd_a3sp>;
120 		#address-cells = <1>;
121 		#size-cells = <0>;
122 		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
125 		clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
126 		power-domains = <&pd_a3sp>;
132 		compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1";
142 		clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
143 		clock-names = "fck";
144 		power-domains = <&pd_c5>;
148 	irqc0: interrupt-controller@e61c0000 {
149 		compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
150 		#interrupt-cells = <2>;
151 		interrupt-controller;
185 		clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
186 		power-domains = <&pd_c4>;
189 	irqc1: interrupt-controller@e61c0200 {
190 		compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
191 		#interrupt-cells = <2>;
192 		interrupt-controller;
220 		clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
221 		power-domains = <&pd_c4>;
225 		compatible = "renesas,pfc-r8a73a4";
227 		gpio-controller;
228 		#gpio-cells = <2>;
229 		gpio-ranges =
236 		interrupts-extended =
252 		power-domains = <&pd_c5>;
256 		compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
260 		clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
261 		power-domains = <&pd_c5>;
265 		#address-cells = <1>;
266 		#size-cells = <0>;
267 		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
270 		clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
271 		power-domains = <&pd_a3sp>;
276 		#address-cells = <1>;
277 		#size-cells = <0>;
278 		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
281 		clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
282 		power-domains = <&pd_a3sp>;
287 		#address-cells = <1>;
288 		#size-cells = <0>;
289 		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
292 		clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
293 		power-domains = <&pd_a3sp>;
298 		#address-cells = <1>;
299 		#size-cells = <0>;
300 		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
303 		clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
304 		power-domains = <&pd_a3sp>;
309 		#address-cells = <1>;
310 		#size-cells = <0>;
311 		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
314 		clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
315 		power-domains = <&pd_a3sp>;
320 		#address-cells = <1>;
321 		#size-cells = <0>;
322 		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
325 		clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
326 		power-domains = <&pd_a3sp>;
331 		#address-cells = <1>;
332 		#size-cells = <0>;
333 		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
336 		clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
337 		power-domains = <&pd_a3sp>;
342 		#address-cells = <1>;
343 		#size-cells = <0>;
344 		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
347 		clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
348 		power-domains = <&pd_a3sp>;
353 		compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
356 		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
357 		clock-names = "fck";
358 		power-domains = <&pd_a3sp>;
363 		compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
366 		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
367 		clock-names = "fck";
368 		power-domains = <&pd_a3sp>;
373 		compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
376 		clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
377 		clock-names = "fck";
378 		power-domains = <&pd_a3sp>;
383 		compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
386 		clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
387 		clock-names = "fck";
388 		power-domains = <&pd_a3sp>;
393 		compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
396 		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
397 		clock-names = "fck";
398 		power-domains = <&pd_a3sp>;
403 		compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
406 		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
407 		clock-names = "fck";
408 		power-domains = <&pd_c4>;
413 		compatible = "renesas,sdhi-r8a73a4";
416 		clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
417 		power-domains = <&pd_a3sp>;
418 		cap-sd-highspeed;
423 		compatible = "renesas,sdhi-r8a73a4";
426 		clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
427 		power-domains = <&pd_a3sp>;
428 		cap-sd-highspeed;
433 		compatible = "renesas,sdhi-r8a73a4";
436 		clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
437 		power-domains = <&pd_a3sp>;
438 		cap-sd-highspeed;
443 		compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
446 		clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
447 		power-domains = <&pd_a3sp>;
448 		reg-io-width = <4>;
453 		compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
456 		clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
457 		power-domains = <&pd_a3sp>;
458 		reg-io-width = <4>;
462 	gic: interrupt-controller@f1001000 {
463 		compatible = "arm,gic-400";
464 		#interrupt-cells = <3>;
465 		#address-cells = <0>;
466 		interrupt-controller;
472 		clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
473 		clock-names = "clk";
474 		power-domains = <&pd_c4>;
478 		compatible = "renesas,bsc-r8a73a4", "renesas,bsc",
479 			     "simple-pm-bus";
480 		#address-cells = <1>;
481 		#size-cells = <1>;
484 		clocks = <&zb_clk>;
485 		power-domains = <&pd_c4>;
488 	clocks {
489 		#address-cells = <2>;
490 		#size-cells = <2>;
493 		/* External root clocks */
495 			compatible = "fixed-clock";
496 			#clock-cells = <0>;
497 			clock-frequency = <32768>;
500 			compatible = "fixed-clock";
501 			#clock-cells = <0>;
502 			clock-frequency = <25000000>;
505 			compatible = "fixed-clock";
506 			#clock-cells = <0>;
507 			clock-frequency = <48000000>;
510 			compatible = "fixed-clock";
511 			#clock-cells = <0>;
513 			clock-frequency = <0>;
516 			compatible = "fixed-clock";
517 			#clock-cells = <0>;
519 			clock-frequency = <0>;
522 		/* Special CPG clocks */
524 			compatible = "renesas,r8a73a4-cpg-clocks";
526 			clocks = <&extal1_clk>, <&extal2_clk>;
527 			#clock-cells = <1>;
528 			clock-output-names = "main", "pll0", "pll1", "pll2",
534 		/* Variable factor clocks (DIV6) */
536 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
538 			clocks = <&pll1_div2_clk>, <0>,
540 			#clock-cells = <0>;
541 			clock-output-names = "zb";
544 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
546 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
548 			#clock-cells = <0>;
551 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
553 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
555 			#clock-cells = <0>;
558 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
560 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
562 			#clock-cells = <0>;
565 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
567 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
569 			#clock-cells = <0>;
572 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
574 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
576 			#clock-cells = <0>;
579 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
581 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
584 			#clock-cells = <0>;
587 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
589 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
592 			#clock-cells = <0>;
595 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
597 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
600 			#clock-cells = <0>;
603 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
605 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
608 			#clock-cells = <0>;
611 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
613 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
616 			#clock-cells = <0>;
619 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
621 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
623 			#clock-cells = <0>;
626 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
628 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
630 			#clock-cells = <0>;
633 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
635 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
637 			#clock-cells = <0>;
640 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
642 			clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
643 			#clock-cells = <0>;
646 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
648 			clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
650 			#clock-cells = <0>;
653 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
655 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
657 			#clock-cells = <0>;
660 		/* Fixed factor clocks */
662 			compatible = "fixed-factor-clock";
663 			clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
664 			#clock-cells = <0>;
665 			clock-div = <2>;
666 			clock-mult = <1>;
669 			compatible = "fixed-factor-clock";
670 			clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
671 			#clock-cells = <0>;
672 			clock-div = <2>;
673 			clock-mult = <1>;
676 			compatible = "fixed-factor-clock";
677 			clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
678 			#clock-cells = <0>;
679 			clock-div = <2>;
680 			clock-mult = <1>;
683 			compatible = "fixed-factor-clock";
684 			clocks = <&extal1_clk>;
685 			#clock-cells = <0>;
686 			clock-div = <2>;
687 			clock-mult = <1>;
690 		/* Gate clocks */
692 			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
694 			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
696 			#clock-cells = <1>;
697 			clock-indices = <
703 			clock-output-names =
708 			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
710 			clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
716 			#clock-cells = <1>;
717 			clock-indices = <
725 			clock-output-names =
731 			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
733 			clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,
737 			#clock-cells = <1>;
738 			clock-indices = <
743 			clock-output-names =
744 				"irqc", "intc-sys", "iic5", "iic4", "iic3";
747 			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
749 			clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
750 			#clock-cells = <1>;
751 			clock-indices = <
754 			clock-output-names =
764 	sysc: system-controller@e6180000 {
765 		compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
768 		pm-domains {
770 				#address-cells = <1>;
771 				#size-cells = <0>;
772 				#power-domain-cells = <0>;
776 					#address-cells = <1>;
777 					#size-cells = <0>;
778 					#power-domain-cells = <0>;
782 						#power-domain-cells = <0>;
787 						#power-domain-cells = <0>;
792 						#address-cells = <1>;
793 						#size-cells = <0>;
794 						#power-domain-cells = <0>;
798 							#power-domain-cells = <0>;
804 						#address-cells = <1>;
805 						#size-cells = <0>;
806 						#power-domain-cells = <0>;
810 							#power-domain-cells = <0>;
816 						#address-cells = <1>;
817 						#size-cells = <0>;
818 						#power-domain-cells = <0>;
822 							#power-domain-cells = <0>;
829 					#power-domain-cells = <0>;
834 					#power-domain-cells = <0>;
839 					#power-domain-cells = <0>;
844 					#address-cells = <1>;
845 					#size-cells = <0>;
846 					#power-domain-cells = <0>;
850 						#power-domain-cells = <0>;
856 					#power-domain-cells = <0>;
861 					#power-domain-cells = <0>;
866 					#address-cells = <1>;
867 					#size-cells = <0>;
868 					#power-domain-cells = <0>;
872 						#power-domain-cells = <0>;
877 						#power-domain-cells = <0>;
883 					#power-domain-cells = <0>;
888 					#address-cells = <1>;
889 					#size-cells = <0>;
890 					#power-domain-cells = <0>;
894 						#power-domain-cells = <0>;
899 						#power-domain-cells = <0>;