Lines Matching +full:axi +full:- +full:config
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
6 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
17 interrupt-parent = <&intc>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 enable-method = "qcom,kpss-acc-v1";
28 next-level-cache = <&L2>;
35 enable-method = "qcom,kpss-acc-v1";
38 next-level-cache = <&L2>;
43 L2: l2-cache {
45 cache-level = <2>;
54 cpu-pmu {
55 compatible = "qcom,krait-pmu";
60 reserved-memory {
61 #address-cells = <1>;
62 #size-cells = <1>;
67 no-map;
72 no-map;
78 compatible = "fixed-clock";
79 #clock-cells = <0>;
80 clock-frequency = <25000000>;
84 compatible = "fixed-clock";
85 #clock-cells = <0>;
86 clock-frequency = <25000000>;
90 compatible = "fixed-clock";
91 clock-frequency = <32768>;
92 #clock-cells = <0>;
98 compatible = "qcom,scm-ipq806x", "qcom,scm";
103 #address-cells = <1>;
104 #size-cells = <1>;
106 compatible = "simple-bus";
109 compatible = "qcom,lpass-cpu";
114 clock-names = "ahbix-clk",
115 "mi2s-osr-clk",
116 "mi2s-bit-clk";
118 interrupt-names = "lpass-irq-lpaif";
120 reg-names = "lpass-lpaif";
124 compatible = "qcom,ipq8064-pinctrl";
127 gpio-controller;
128 gpio-ranges = <&qcom_pinmux 0 0 69>;
129 #gpio-cells = <2>;
130 interrupt-controller;
131 #interrupt-cells = <2>;
138 drive-strength = <12>;
139 bias-disable;
147 drive-strength = <12>;
148 bias-disable;
156 drive-strength = <12>;
157 bias-disable;
165 drive-strength = <10>;
166 bias-none;
175 drive-strength = <2>;
176 bias-pull-down;
177 output-low;
184 drive-strength = <2>;
185 bias-pull-up;
190 intc: interrupt-controller@2000000 {
191 compatible = "qcom,msm-qgic2";
192 interrupt-controller;
193 #interrupt-cells = <3>;
199 compatible = "qcom,kpss-timer",
200 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
212 clock-frequency = <25000000>,
215 clock-names = "sleep";
216 cpu-offset = <0x80000>;
219 acc0: clock-controller@2088000 {
220 compatible = "qcom,kpss-acc-v1";
224 acc1: clock-controller@2098000 {
225 compatible = "qcom,kpss-acc-v1";
242 compatible = "qcom,gsbi-v1.0.0";
243 cell-index = <2>;
246 clock-names = "iface";
247 #address-cells = <1>;
248 #size-cells = <1>;
252 syscon-tcsr = <&tcsr>;
255 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
260 clock-names = "core", "iface";
265 compatible = "qcom,i2c-qup-v1.1.1";
270 clock-names = "core", "iface";
273 #address-cells = <1>;
274 #size-cells = <0>;
280 compatible = "qcom,gsbi-v1.0.0";
281 cell-index = <4>;
284 clock-names = "iface";
285 #address-cells = <1>;
286 #size-cells = <1>;
290 syscon-tcsr = <&tcsr>;
293 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
298 clock-names = "core", "iface";
303 compatible = "qcom,i2c-qup-v1.1.1";
308 clock-names = "core", "iface";
311 #address-cells = <1>;
312 #size-cells = <0>;
317 compatible = "qcom,gsbi-v1.0.0";
318 cell-index = <5>;
321 clock-names = "iface";
322 #address-cells = <1>;
323 #size-cells = <1>;
327 syscon-tcsr = <&tcsr>;
330 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
335 clock-names = "core", "iface";
340 compatible = "qcom,i2c-qup-v1.1.1";
345 clock-names = "core", "iface";
348 #address-cells = <1>;
349 #size-cells = <0>;
353 compatible = "qcom,spi-qup-v1.1.1";
358 clock-names = "core", "iface";
361 #address-cells = <1>;
362 #size-cells = <0>;
368 compatible = "qcom,gsbi-v1.0.0";
369 cell-index = <7>;
372 clock-names = "iface";
373 #address-cells = <1>;
374 #size-cells = <1>;
376 syscon-tcsr = <&tcsr>;
379 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
384 clock-names = "core", "iface";
389 sata_phy: sata-phy@1b400000 {
390 compatible = "qcom,ipq806x-sata-phy";
394 clock-names = "cfg";
396 #phy-cells = <0>;
401 compatible = "qcom,ipq806x-ahci", "generic-ahci";
411 clock-names = "slave_face", "iface", "core",
414 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
415 assigned-clock-rates = <100000000>, <100000000>;
418 phy-names = "sata-phy";
425 qcom,controller-type = "pmic-arbiter";
431 #address-cells = <1>;
432 #size-cells = <1>;
435 gcc: clock-controller@900000 {
436 compatible = "qcom,gcc-ipq8064";
438 #clock-cells = <1>;
439 #reset-cells = <1>;
443 compatible = "qcom,tcsr-ipq8064", "syscon";
447 lcc: clock-controller@28000000 {
448 compatible = "qcom,lcc-ipq8064";
450 #clock-cells = <1>;
451 #reset-cells = <1>;
455 compatible = "qcom,pcie-ipq8064";
460 reg-names = "dbi", "elbi", "parf", "config";
462 linux,pci-domain = <0>;
463 bus-range = <0x00 0xff>;
464 num-lanes = <1>;
465 #address-cells = <3>;
466 #size-cells = <2>;
469 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
472 interrupt-names = "msi";
473 #interrupt-cells = <1>;
474 interrupt-map-mask = <0 0 0 0x7>;
475 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
485 clock-names = "core", "iface", "phy", "aux", "ref";
487 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
488 assigned-clock-rates = <100000000>;
496 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
498 pinctrl-0 = <&pcie0_pins>;
499 pinctrl-names = "default";
502 perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
506 compatible = "qcom,pcie-ipq8064";
511 reg-names = "dbi", "elbi", "parf", "config";
513 linux,pci-domain = <1>;
514 bus-range = <0x00 0xff>;
515 num-lanes = <1>;
516 #address-cells = <3>;
517 #size-cells = <2>;
520 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
523 interrupt-names = "msi";
524 #interrupt-cells = <1>;
525 interrupt-map-mask = <0 0 0 0x7>;
526 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
536 clock-names = "core", "iface", "phy", "aux", "ref";
538 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
539 assigned-clock-rates = <100000000>;
547 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
549 pinctrl-0 = <&pcie1_pins>;
550 pinctrl-names = "default";
553 perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
557 compatible = "qcom,pcie-ipq8064";
562 reg-names = "dbi", "elbi", "parf", "config";
564 linux,pci-domain = <2>;
565 bus-range = <0x00 0xff>;
566 num-lanes = <1>;
567 #address-cells = <3>;
568 #size-cells = <2>;
571 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
574 interrupt-names = "msi";
575 #interrupt-cells = <1>;
576 interrupt-map-mask = <0 0 0 0x7>;
577 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
587 clock-names = "core", "iface", "phy", "aux", "ref";
589 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
590 assigned-clock-rates = <100000000>;
598 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
600 pinctrl-0 = <&pcie2_pins>;
601 pinctrl-names = "default";
604 perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
617 stmmac_axi_setup: stmmac-axi-config {
625 compatible = "qcom,ipq806x-gmac";
628 interrupt-names = "macirq";
630 snps,axi-config = <&stmmac_axi_setup>;
634 qcom,nss-common = <&nss_common>;
635 qcom,qsgmii-csr = <&qsgmii_csr>;
638 clock-names = "stmmaceth";
641 reset-names = "stmmaceth";
648 compatible = "qcom,ipq806x-gmac";
651 interrupt-names = "macirq";
653 snps,axi-config = <&stmmac_axi_setup>;
657 qcom,nss-common = <&nss_common>;
658 qcom,qsgmii-csr = <&qsgmii_csr>;
661 clock-names = "stmmaceth";
664 reset-names = "stmmaceth";
671 compatible = "qcom,ipq806x-gmac";
674 interrupt-names = "macirq";
676 snps,axi-config = <&stmmac_axi_setup>;
680 qcom,nss-common = <&nss_common>;
681 qcom,qsgmii-csr = <&qsgmii_csr>;
684 clock-names = "stmmaceth";
687 reset-names = "stmmaceth";
694 compatible = "qcom,ipq806x-gmac";
697 interrupt-names = "macirq";
699 snps,axi-config = <&stmmac_axi_setup>;
703 qcom,nss-common = <&nss_common>;
704 qcom,qsgmii-csr = <&qsgmii_csr>;
707 clock-names = "stmmaceth";
710 reset-names = "stmmaceth";
715 vsdcc_fixed: vsdcc-regulator {
716 compatible = "regulator-fixed";
717 regulator-name = "SDCC Power";
718 regulator-min-microvolt = <3300000>;
719 regulator-max-microvolt = <3300000>;
720 regulator-always-on;
724 compatible = "qcom,bam-v1.3.0";
728 clock-names = "bam_clk";
729 #dma-cells = <1>;
734 compatible = "qcom,bam-v1.3.0";
738 clock-names = "bam_clk";
739 #dma-cells = <1>;
744 compatible = "simple-bus";
745 #address-cells = <1>;
746 #size-cells = <1>;
752 arm,primecell-periphid = <0x00051180>;
755 interrupt-names = "cmd_irq";
757 clock-names = "mclk", "apb_pclk";
758 bus-width = <8>;
759 max-frequency = <96000000>;
760 non-removable;
761 cap-sd-highspeed;
762 cap-mmc-highspeed;
763 mmc-ddr-1_8v;
764 vmmc-supply = <&vsdcc_fixed>;
766 dma-names = "tx", "rx";
771 arm,primecell-periphid = <0x00051180>;
775 interrupt-names = "cmd_irq";
777 clock-names = "mclk", "apb_pclk";
778 bus-width = <8>;
779 cap-sd-highspeed;
780 cap-mmc-highspeed;
781 max-frequency = <192000000>;
782 #mmc-ddr-1_8v;
783 sd-uhs-sdr104;
784 sd-uhs-ddr50;
785 vqmmc-supply = <&vsdcc_fixed>;
787 dma-names = "tx", "rx";