Lines Matching +full:0 +full:x400
32 #address-cells = <0>;
33 #size-cells = <0>;
64 reg = <0x480a6000 0x50>;
72 reg = <0x480b2000 0x1000>;
80 reg = <0x480FE000 0x1000>;
85 reg = <0x48056000 0x4>,
86 <0x4805602c 0x4>,
87 <0x48056028 0x4>;
101 ranges = <0 0x48056000 0x1000>;
103 sdma: dma-controller@0 {
105 reg = <0 0x1000>;
119 reg = <0x48070000 0x80>;
121 #size-cells = <0>;
130 reg = <0x48072000 0x80>;
132 #size-cells = <0>;
141 reg = <0x48098000 0x100>;
152 reg = <0x4809a000 0x100>;
161 reg = <0x480a0000 0x50>;
168 reg = <0x480a4000 0x64>;
177 reg = <0x4806a000 0x2000>;
187 reg = <0x4806c000 0x400>;
197 reg = <0x4806e000 0x400>;
206 reg = <0x4802a000 0x4>,
207 <0x4802a010 0x4>,
208 <0x4802a014 0x4>;
223 ranges = <0x0 0x4802a000 0x1000>;
225 timer2: timer@0 {
227 reg = <0 0x400>;
234 reg = <0x48078000 0x400>;
241 reg = <0x4807a000 0x400>;
248 reg = <0x4807c000 0x400>;
256 reg = <0x4807e000 0x400>;
264 reg = <0x48080000 0x400>;
272 reg = <0x48082000 0x400>;
280 reg = <0x48084000 0x400>;
288 reg = <0x48086000 0x400>;
296 reg = <0x48088000 0x400>;
304 reg = <0x4808a000 0x400>;
312 reg = <0x48050000 0x400>;
321 reg = <0x48050400 0x400>;
328 reg = <0x48050800 0x400>;
335 reg = <0x48050c00 0x400>;