boot/dts/mt8135.dtsi

1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8135-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/mt8135-resets.h>
12 #include "mt8135-pinfunc.h"
15 	#address-cells = <2>;
16 	#size-cells = <2>;
18 	interrupt-parent = <&sysirq>;
20 	cpu-map {
41 		#address-cells = <1>;
42 		#size-cells = <0>;
43 		enable-method = "mediatek,mt81xx-tz-smp";
47 			compatible = "arm,cortex-a7";
48 			reg = <0x000>;
53 			compatible = "arm,cortex-a7";
54 			reg = <0x001>;
59 			compatible = "arm,cortex-a15";
60 			reg = <0x100>;
65 			compatible = "arm,cortex-a15";
66 			reg = <0x101>;
70 	reserved-memory {
71 		#address-cells = <2>;
72 		#size-cells = <2>;
75 		trustzone-bootinfo@80002000 {
76 			compatible = "mediatek,trustzone-bootinfo";
77 			reg = <0 0x80002000 0 0x1000>;
82 		#address-cells = <2>;
83 		#size-cells = <2>;
84 		compatible = "simple-bus";
88 			compatible = "fixed-clock";
89 			clock-frequency = <13000000>;
90 			#clock-cells = <0>;
94 			compatible = "fixed-clock";
95 			clock-frequency = <32000>;
96 			#clock-cells = <0>;
100 			compatible = "fixed-clock";
101 			#clock-cells = <0>;
102 			clock-frequency = <26000000>;
107 		compatible = "arm,armv7-timer";
108 		interrupt-parent = <&gic>;
117 		clock-frequency = <13000000>;
118 		arm,cpu-registers-not-fw-configured;
122 		#address-cells = <2>;
123 		#size-cells = <2>;
124 		compatible = "simple-bus";
128 			compatible = "mediatek,mt8135-topckgen";
129 			reg = <0 0x10000000 0 0x1000>;
130 			#clock-cells = <1>;
134 			#reset-cells = <1>;
135 			#clock-cells = <1>;
136 			compatible = "mediatek,mt8135-infracfg", "syscon";
137 			reg = <0 0x10001000 0 0x1000>;
141 			#reset-cells = <1>;
142 			#clock-cells = <1>;
143 			compatible = "mediatek,mt8135-pericfg", "syscon";
144 			reg = <0 0x10003000 0 0x1000>;
152 			compatible = "mediatek,mt8135-pinctrl";
153 			reg = <0 0x1000b000 0 0x1000>;
154 			mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
155 			pins-are-numbered;
156 			gpio-controller;
157 			#gpio-cells = <2>;
158 			interrupt-controller;
159 			#interrupt-cells = <2>;
166 			compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
167 			reg = <0 0x10005000 0 0x1000>;
171 			compatible = "mediatek,mt8135-timer",
172 					"mediatek,mt6577-timer";
173 			reg = <0 0x10008000 0 0x80>;
176 			clock-names = "system-clk", "rtc-clk";
180 			compatible = "mediatek,mt8135-pwrap";
181 			reg = <0 0x1000f000 0 0x1000>,
183 			reg-names = "pwrap", "pwrap-bridge";
187 			reset-names = "pwrap", "pwrap-bridge";
189 			clock-names = "spi", "wrap";
192 		sysirq: interrupt-controller@10200030 {
193 			compatible = "mediatek,mt8135-sysirq",
194 				     "mediatek,mt6577-sysirq";
195 			interrupt-controller;
196 			#interrupt-cells = <3>;
197 			interrupt-parent = <&gic>;
198 			reg = <0 0x10200030 0 0x1c>;
202 			compatible = "mediatek,mt8135-apmixedsys";
203 			reg = <0 0x10209000 0 0x1000>;
204 			#clock-cells = <1>;
208 			compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
209 			reg = <0 0x1020c000 0 0x1000>;
212 		gic: interrupt-controller@10211000 {
213 			compatible = "arm,cortex-a15-gic";
214 			interrupt-controller;
215 			#interrupt-cells = <3>;
216 			interrupt-parent = <&gic>;
217 			reg = <0 0x10211000 0 0x1000>,
224 			compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
225 			reg = <0 0x11006000 0 0x400>;
228 			clock-names = "baud", "bus";
233 			compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
234 			reg = <0 0x11007000 0 0x400>;
237 			clock-names = "baud", "bus";
242 			compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
243 			reg = <0 0x11008000 0 0x400>;
246 			clock-names = "baud", "bus";
251 			compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
252 			reg = <0 0x11009000 0 0x400>;
255 			clock-names = "baud", "bus";