boot/dts/meson8.dtsi

6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
28 			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
30 			clocks = <&clkc CLKID_CPUCLK>;
39 			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
41 			clocks = <&clkc CLKID_CPUCLK>;
50 			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
52 			clocks = <&clkc CLKID_CPUCLK>;
61 			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
63 			clocks = <&clkc CLKID_CPUCLK>;
201 			compatible = "amlogic,meson8-ddr-clkc";
254 			clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
453 	clocks = <&clkc CLKID_EFUSE>;
463 	clocks = <&clkc CLKID_ETH>;
475 	clkc: clock-controller {  label
476 		compatible = "amlogic,meson8-clkc";
487 		clocks = <&clkc CLKID_VPU>;
489 		assigned-clocks = <&clkc CLKID_VPU>;
496 	clocks = <&clkc CLKID_RNG0>;
501 	clocks = <&clkc CLKID_CLK81>;
505 	clocks = <&clkc CLKID_CLK81>;
509 	clocks = <&clkc CLKID_CLK81>;
531 		clocks = <&clkc CLKID_PERIPH>;
544 		clocks = <&clkc CLKID_PERIPH>;
563 	clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
573 		 <&clkc CLKID_FCLK_DIV4>,
574 		 <&clkc CLKID_FCLK_DIV3>,
575 		 <&clkc CLKID_FCLK_DIV5>,
576 		 <&clkc CLKID_SDHC>;
582 	clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
587 	clocks = <&clkc CLKID_CLK81>;
591 	clocks = <&xtal>, <&clkc CLKID_CLK81>;
597 	clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>;
603 	clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>;
609 	clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>;
615 	clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>;
621 	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
627 	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
633 	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
640 	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;