Lines Matching +full:0 +full:x00000042
74 #size-cells = <0>;
79 reg = <0xf00>;
80 clocks = <&clockgen 1 0>;
87 reg = <0xf01>;
88 clocks = <&clockgen 1 0>;
95 reg = <0x0 0x0 0x0 0x0>;
100 #clock-cells = <0>;
123 offset = <0xb0>;
124 mask = <0x02>;
137 reg = <0x0 0x1080000 0x0 0x1000>;
146 reg = <0x0 0x1401000 0x0 0x1000>,
147 <0x0 0x1402000 0x0 0x2000>,
148 <0x0 0x1404000 0x0 0x2000>,
149 <0x0 0x1406000 0x0 0x2000>;
156 reg = <0x0 0x1570e00 0x0 0x8>;
163 reg = <0x0 0x1570e08 0x0 0x8>;
170 reg = <0x0 0x1530000 0x0 0x10000>;
176 reg = <0x0 0x1ee0000 0x0 0x10000>;
183 #size-cells = <0>;
184 reg = <0x0 0x1550000 0x0 0x10000>,
185 <0x0 0x40000000 0x0 0x20000000>;
195 reg = <0x0 0x1560000 0x0 0x10000>;
197 clock-frequency = <0>;
207 reg = <0x0 0x3200000 0x0 0x10000>,
208 <0x0 0x20220520 0x0 0x4>;
218 reg = <0x0 0x1570000 0x0 0x10000>;
222 ranges = <0x0 0x0 0x1570000 0x10000>;
227 #address-cells = <0>;
229 reg = <0x1ac 4>;
231 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
232 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
233 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
234 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
235 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
236 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
237 interrupt-map-mask = <0xffffffff 0x0>;
242 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
246 reg = <0x0 0x1700000 0x0 0x100000>;
247 ranges = <0x0 0x0 0x1700000 0x100000>;
251 compatible = "fsl,sec-v5.0-job-ring",
252 "fsl,sec-v4.0-job-ring";
253 reg = <0x10000 0x10000>;
258 compatible = "fsl,sec-v5.0-job-ring",
259 "fsl,sec-v4.0-job-ring";
260 reg = <0x20000 0x10000>;
265 compatible = "fsl,sec-v5.0-job-ring",
266 "fsl,sec-v4.0-job-ring";
267 reg = <0x30000 0x10000>;
272 compatible = "fsl,sec-v5.0-job-ring",
273 "fsl,sec-v4.0-job-ring";
274 reg = <0x40000 0x10000>;
282 reg = <0x0 0x1ee1000 0x0 0x1000>;
289 reg = <0x0 0x1f00000 0x0 0x10000>;
291 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>;
292 fsl,tmu-calibration = <0x00000000 0x0000000f
293 0x00000001 0x00000017
294 0x00000002 0x0000001e
295 0x00000003 0x00000026
296 0x00000004 0x0000002e
297 0x00000005 0x00000035
298 0x00000006 0x0000003d
299 0x00000007 0x00000044
300 0x00000008 0x0000004c
301 0x00000009 0x00000053
302 0x0000000a 0x0000005b
303 0x0000000b 0x00000064
305 0x00010000 0x00000011
306 0x00010001 0x0000001c
307 0x00010002 0x00000024
308 0x00010003 0x0000002b
309 0x00010004 0x00000034
310 0x00010005 0x00000039
311 0x00010006 0x00000042
312 0x00010007 0x0000004c
313 0x00010008 0x00000051
314 0x00010009 0x0000005a
315 0x0001000a 0x00000063
317 0x00020000 0x00000013
318 0x00020001 0x00000019
319 0x00020002 0x00000024
320 0x00020003 0x0000002c
321 0x00020004 0x00000035
322 0x00020005 0x0000003d
323 0x00020006 0x00000046
324 0x00020007 0x00000050
325 0x00020008 0x00000059
327 0x00030000 0x00000002
328 0x00030001 0x0000000d
329 0x00030002 0x00000019
330 0x00030003 0x00000024>;
339 thermal-sensors = <&tmu 0>;
368 compatible = "fsl,ls1021a-v1.0-dspi";
370 #size-cells = <0>;
371 reg = <0x0 0x2100000 0x0 0x10000>;
381 compatible = "fsl,ls1021a-v1.0-dspi";
383 #size-cells = <0>;
384 reg = <0x0 0x2110000 0x0 0x10000>;
396 #size-cells = <0>;
397 reg = <0x0 0x2180000 0x0 0x10000>;
409 #size-cells = <0>;
410 reg = <0x0 0x2190000 0x0 0x10000>;
422 #size-cells = <0>;
423 reg = <0x0 0x21a0000 0x0 0x10000>;
434 reg = <0x0 0x21c0500 0x0 0x100>;
436 clock-frequency = <0>;
443 reg = <0x0 0x21c0600 0x0 0x100>;
445 clock-frequency = <0>;
452 reg = <0x0 0x21d0500 0x0 0x100>;
454 clock-frequency = <0>;
461 reg = <0x0 0x21d0600 0x0 0x100>;
463 clock-frequency = <0>;
470 reg = <0x0 0x29d0000 0x0 0x10000>;
477 reg = <0x0 0x29e0000 0x0 0x10000>;
484 reg = <0x0 0x29f0000 0x0 0x10000>;
491 reg = <0x0 0x2a00000 0x0 0x10000>;
498 reg = <0x0 0x2300000 0x0 0x10000>;
508 reg = <0x0 0x2310000 0x0 0x10000>;
518 reg = <0x0 0x2320000 0x0 0x10000>;
528 reg = <0x0 0x2330000 0x0 0x10000>;
538 reg = <0x0 0x2950000 0x0 0x1000>;
547 reg = <0x0 0x2960000 0x0 0x1000>;
556 reg = <0x0 0x2970000 0x0 0x1000>;
565 reg = <0x0 0x2980000 0x0 0x1000>;
574 reg = <0x0 0x2990000 0x0 0x1000>;
583 reg = <0x0 0x29a0000 0x0 0x1000>;
593 reg = <0x0 0x29d0000 0x0 0x10000>;
605 reg = <0x0 0x29e0000 0x0 0x10000>;
617 reg = <0x0 0x29f0000 0x0 0x10000>;
629 reg = <0x0 0x2a00000 0x0 0x10000>;
641 reg = <0x0 0x2a10000 0x0 0x10000>;
653 reg = <0x0 0x2a20000 0x0 0x10000>;
665 reg = <0x0 0x2a30000 0x0 0x10000>;
677 reg = <0x0 0x2a40000 0x0 0x10000>;
688 reg = <0x0 0x2ad0000 0x0 0x10000>;
696 #sound-dai-cells = <0>;
698 reg = <0x0 0x2b50000 0x0 0x10000>;
710 #sound-dai-cells = <0>;
712 reg = <0x0 0x2b60000 0x0 0x10000>;
726 reg = <0x0 0x2c00000 0x0 0x10000>,
727 <0x0 0x2c10000 0x0 0x10000>,
728 <0x0 0x2c20000 0x0 0x10000>;
741 reg = <0x0 0x2ce0000 0x0 0x10000>;
743 clocks = <&clockgen 4 0>,
744 <&clockgen 4 0>;
754 #size-cells = <0>;
755 reg = <0x0 0x2d24000 0x0 0x4000>,
756 <0x0 0x2d10030 0x0 0x4>;
763 #size-cells = <0>;
764 reg = <0x0 0x2d64000 0x0 0x4000>,
765 <0x0 0x2d50030 0x0 0x4>;
770 reg = <0x0 0x2d10e00 0x0 0xb0>;
774 fsl,tmr-add = <0xaaaaaaab>;
795 reg = <0x0 0x2d10000 0x0 0x1000>;
804 reg = <0x0 0x2d14000 0x0 0x1000>;
824 reg = <0x0 0x2d50000 0x0 0x1000>;
833 reg = <0x0 0x2d54000 0x0 0x1000>;
853 reg = <0x0 0x2d90000 0x0 0x1000>;
862 reg = <0x0 0x2d94000 0x0 0x1000>;
871 reg = <0x0 0x8600000 0x0 0x1000>;
879 reg = <0x0 0x3100000 0x0 0x10000>;
882 snps,quirk-frame-length-adjustment = <0x20>;
889 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
890 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
893 fsl,pcie-scfg = <&scfg 0>;
898 bus-range = <0x0 0xff>;
899 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
900 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
903 interrupt-map-mask = <0 0 0 7>;
904 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
905 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
906 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
907 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
913 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
914 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
922 bus-range = <0x0 0xff>;
923 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
924 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
927 interrupt-map-mask = <0 0 0 7>;
928 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
929 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
930 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
931 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
937 reg = <0x0 0x2a70000 0x0 0x1000>;
946 reg = <0x0 0x2a80000 0x0 0x1000>;
955 reg = <0x0 0x2a90000 0x0 0x1000>;
964 reg = <0x0 0x2aa0000 0x0 0x1000>;
973 reg = <0x0 0x10000000 0x0 0x10000>;
976 ranges = <0x0 0x0 0x10000000 0x10000>;
981 reg = <0x0 0x10010000 0x0 0x10000>;
984 ranges = <0x0 0x0 0x10010000 0x10000>;
989 reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
990 <0x0 0x8389000 0x0 0x1000>, /* Status regs */
991 <0x0 0x838a000 0x0 0x2000>; /* Block regs */
999 block-offset = <0x1000>;
1008 reg = <0x0 0x1ee2140 0x0 0x8>;
1014 reg = <0x0 0x29d0000 0x0 0x10000>;
1016 fsl,rcpm-wakeup = <&rcpm 0x20000 0x0>;