boot/dts/imx7ulp.dtsi

132 				 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
155 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
167 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
176 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
186 			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
222 			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
223 				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
236 			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
237 				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
246 		scg1: clock-controller@403e0000 {  label
247 			compatible = "fsl,imx7ulp-scg1";
262 			assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
270 			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
271 				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
272 				 <&scg1 IMX7ULP_CLK_DDR_DIV>,
273 				 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
274 				 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
275 				 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
276 				 <&scg1 IMX7ULP_CLK_UPLL>,
277 				 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
278 				 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
279 				 <&scg1 IMX7ULP_CLK_ROSC>,
280 				 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
286 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
293 			clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
294 				 <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
302 			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
303 				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
304 				 <&scg1 IMX7ULP_CLK_DDR_DIV>,
305 				 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
306 				 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
307 				 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
308 				 <&scg1 IMX7ULP_CLK_UPLL>,
309 				 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
310 				 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
311 				 <&scg1 IMX7ULP_CLK_ROSC>,
312 				 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
334 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
346 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
358 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
370 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
458 			clocks = <&scg1 IMX7ULP_CLK_DUMMY>;