Lines Matching full:clks
75 clocks = <&clks IMX7D_CLK_ARM>;
96 clocks = <&clks IMX7D_USB_PHY1_CLK>;
103 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
169 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
196 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
211 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
246 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
269 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
284 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
403 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
410 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
418 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
426 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
440 clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
441 <&clks IMX7D_GPT1_ROOT_CLK>;
449 clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
450 <&clks IMX7D_GPT2_ROOT_CLK>;
459 clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
460 <&clks IMX7D_GPT3_ROOT_CLK>;
469 clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
470 <&clks IMX7D_GPT4_ROOT_CLK>;
479 clocks = <&clks IMX7D_KPP_ROOT_CLK>;
534 clocks = <&clks IMX7D_OCOTP_CLK>;
587 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
601 clocks = <&clks IMX7D_SNVS_CLK>;
609 clocks = <&clks IMX7D_SNVS_CLK>;
617 clks: clock-controller@30380000 { label
679 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
689 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
701 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
702 <&clks IMX7D_ECSPI4_ROOT_CLK>;
711 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
712 <&clks IMX7D_PWM1_ROOT_CLK>;
722 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
723 <&clks IMX7D_PWM2_ROOT_CLK>;
733 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
734 <&clks IMX7D_PWM3_ROOT_CLK>;
744 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
745 <&clks IMX7D_PWM4_ROOT_CLK>;
755 clocks = <&clks IMX7D_CLK_DUMMY>,
756 <&clks IMX7D_CSI_MCLK_ROOT_CLK>,
757 <&clks IMX7D_CLK_DUMMY>;
772 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
773 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
784 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
785 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
786 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
828 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
829 <&clks IMX7D_ECSPI1_ROOT_CLK>;
840 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
841 <&clks IMX7D_ECSPI2_ROOT_CLK>;
852 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
853 <&clks IMX7D_ECSPI3_ROOT_CLK>;
863 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
864 <&clks IMX7D_UART1_ROOT_CLK>;
874 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
875 <&clks IMX7D_UART2_ROOT_CLK>;
885 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
886 <&clks IMX7D_UART3_ROOT_CLK>;
896 clocks = <&clks IMX7D_SAI1_IPG_CLK>,
897 <&clks IMX7D_SAI1_ROOT_CLK>,
898 <&clks IMX7D_CLK_DUMMY>,
899 <&clks IMX7D_CLK_DUMMY>;
911 clocks = <&clks IMX7D_SAI2_IPG_CLK>,
912 <&clks IMX7D_SAI2_ROOT_CLK>,
913 <&clks IMX7D_CLK_DUMMY>,
914 <&clks IMX7D_CLK_DUMMY>;
926 clocks = <&clks IMX7D_SAI3_IPG_CLK>,
927 <&clks IMX7D_SAI3_ROOT_CLK>,
928 <&clks IMX7D_CLK_DUMMY>,
929 <&clks IMX7D_CLK_DUMMY>;
944 clocks = <&clks IMX7D_CAAM_CLK>,
945 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
971 clocks = <&clks IMX7D_CLK_DUMMY>,
972 <&clks IMX7D_CAN1_ROOT_CLK>;
982 clocks = <&clks IMX7D_CLK_DUMMY>,
983 <&clks IMX7D_CAN2_ROOT_CLK>;
995 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
1005 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
1015 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
1025 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
1034 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
1035 <&clks IMX7D_UART4_ROOT_CLK>;
1045 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
1046 <&clks IMX7D_UART5_ROOT_CLK>;
1056 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
1057 <&clks IMX7D_UART6_ROOT_CLK>;
1067 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
1068 <&clks IMX7D_UART7_ROOT_CLK>;
1077 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1086 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1096 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1108 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1133 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1134 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1135 <&clks IMX7D_USDHC1_ROOT_CLK>;
1145 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1146 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1147 <&clks IMX7D_USDHC2_ROOT_CLK>;
1157 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1158 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1159 <&clks IMX7D_USDHC3_ROOT_CLK>;
1172 clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
1173 <&clks IMX7D_QSPI_ROOT_CLK>;
1182 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1183 <&clks IMX7D_SDMA_CORE_CLK>;
1197 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
1198 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1199 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1200 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1201 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1221 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1232 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1233 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1238 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1239 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;