Lines Matching +full:remote +full:- +full:endpoint
1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6q-pinfunc.h"
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
24 operating-points = <
32 fsl,soc-operating-points = <
33 /* ARM kHz SOC-PU uV */
40 clock-latency = <61036>; /* two CLK32 periods */
41 #cooling-cells = <2>;
47 clock-names = "arm", "pll2_pfd2_396m", "step",
49 arm-supply = <®_arm>;
50 pu-supply = <®_pu>;
51 soc-supply = <®_soc>;
52 nvmem-cells = <&cpu_speed_grade>;
53 nvmem-cell-names = "speed_grade";
57 compatible = "arm,cortex-a9";
60 next-level-cache = <&L2>;
61 operating-points = <
69 fsl,soc-operating-points = <
70 /* ARM kHz SOC-PU uV */
77 clock-latency = <61036>; /* two CLK32 periods */
78 #cooling-cells = <2>;
84 clock-names = "arm", "pll2_pfd2_396m", "step",
86 arm-supply = <®_arm>;
87 pu-supply = <®_pu>;
88 soc-supply = <®_soc>;
92 compatible = "arm,cortex-a9";
95 next-level-cache = <&L2>;
96 operating-points = <
104 fsl,soc-operating-points = <
105 /* ARM kHz SOC-PU uV */
112 clock-latency = <61036>; /* two CLK32 periods */
113 #cooling-cells = <2>;
119 clock-names = "arm", "pll2_pfd2_396m", "step",
121 arm-supply = <®_arm>;
122 pu-supply = <®_pu>;
123 soc-supply = <®_soc>;
127 compatible = "arm,cortex-a9";
130 next-level-cache = <&L2>;
131 operating-points = <
139 fsl,soc-operating-points = <
140 /* ARM kHz SOC-PU uV */
147 clock-latency = <61036>; /* two CLK32 periods */
148 #cooling-cells = <2>;
154 clock-names = "arm", "pll2_pfd2_396m", "step",
156 arm-supply = <®_arm>;
157 pu-supply = <®_pu>;
158 soc-supply = <®_soc>;
164 compatible = "mmio-sram";
170 spba-bus@2000000 {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
179 clock-names = "ipg", "per";
181 dma-names = "rx", "tx";
188 compatible = "fsl,imx6q-ahci";
194 clock-names = "sata", "sata_ref", "ahb";
204 clock-names = "bus", "core";
205 power-domains = <&pd_pu>;
206 #cooling-cells = <2>;
210 #address-cells = <1>;
211 #size-cells = <0>;
212 compatible = "fsl,imx6q-ipu";
219 clock-names = "bus", "di0", "di1";
225 ipu2_csi0_from_mipi_vc2: endpoint {
226 remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
233 ipu2_csi1_from_ipu2_csi1_mux: endpoint {
234 remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
239 #address-cells = <1>;
240 #size-cells = <0>;
243 ipu2_di0_disp0: endpoint@0 {
247 ipu2_di0_hdmi: endpoint@1 {
249 remote-endpoint = <&hdmi_mux_2>;
252 ipu2_di0_mipi: endpoint@2 {
254 remote-endpoint = <&mipi_mux_2>;
257 ipu2_di0_lvds0: endpoint@3 {
259 remote-endpoint = <&lvds0_mux_2>;
262 ipu2_di0_lvds1: endpoint@4 {
264 remote-endpoint = <&lvds1_mux_2>;
269 #address-cells = <1>;
270 #size-cells = <0>;
273 ipu2_di1_hdmi: endpoint@1 {
275 remote-endpoint = <&hdmi_mux_3>;
278 ipu2_di1_mipi: endpoint@2 {
280 remote-endpoint = <&mipi_mux_3>;
283 ipu2_di1_lvds0: endpoint@3 {
285 remote-endpoint = <&lvds0_mux_3>;
288 ipu2_di1_lvds1: endpoint@4 {
290 remote-endpoint = <&lvds1_mux_3>;
296 capture-subsystem {
297 compatible = "fsl,imx-capture-subsystem";
301 display-subsystem {
302 compatible = "fsl,imx-display-subsystem";
308 gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
317 gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
322 gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
326 gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
330 gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
335 gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
341 gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
346 compatible = "video-mux";
347 mux-controls = <&mux 0>;
348 #address-cells = <1>;
349 #size-cells = <0>;
354 ipu1_csi0_mux_from_mipi_vc0: endpoint {
355 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
362 ipu1_csi0_mux_from_parallel_sensor: endpoint {
369 ipu1_csi0_mux_to_ipu1_csi0: endpoint {
370 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
376 compatible = "video-mux";
377 mux-controls = <&mux 1>;
378 #address-cells = <1>;
379 #size-cells = <0>;
384 ipu2_csi1_mux_from_mipi_vc3: endpoint {
385 remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
392 ipu2_csi1_mux_from_parallel_sensor: endpoint {
399 ipu2_csi1_mux_to_ipu2_csi1: endpoint {
400 remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
407 compatible = "fsl,imx6q-hdmi";
412 hdmi_mux_2: endpoint {
413 remote-endpoint = <&ipu2_di0_hdmi>;
420 hdmi_mux_3: endpoint {
421 remote-endpoint = <&ipu2_di1_hdmi>;
427 compatible = "fsl,imx6q-iomuxc";
431 ipu1_csi1_from_mipi_vc1: endpoint {
432 remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
441 clock-names = "di0_pll", "di1_pll",
445 lvds-channel@0 {
449 lvds0_mux_2: endpoint {
450 remote-endpoint = <&ipu2_di0_lvds0>;
457 lvds0_mux_3: endpoint {
458 remote-endpoint = <&ipu2_di1_lvds0>;
463 lvds-channel@1 {
467 lvds1_mux_2: endpoint {
468 remote-endpoint = <&ipu2_di0_lvds1>;
475 lvds1_mux_3: endpoint {
476 remote-endpoint = <&ipu2_di1_lvds1>;
486 mipi_vc0_to_ipu1_csi0_mux: endpoint {
487 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
494 mipi_vc1_to_ipu1_csi1: endpoint {
495 remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
502 mipi_vc2_to_ipu2_csi0: endpoint {
503 remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
510 mipi_vc3_to_ipu2_csi1_mux: endpoint {
511 remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
521 mipi_mux_2: endpoint {
522 remote-endpoint = <&ipu2_di0_mipi>;
529 mipi_mux_3: endpoint {
530 remote-endpoint = <&ipu2_di1_mipi>;
537 mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
547 compatible = "fsl,imx6q-vpu", "cnm,coda960";