boot/dts/highbank.dts

1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
14 	#address-cells = <1>;
15 	#size-cells = <1>;
18 		#address-cells = <1>;
19 		#size-cells = <0>;
22 			compatible = "arm,cortex-a9";
24 			reg = <0x900>;
25 			next-level-cache = <&L2>;
27 			clock-names = "cpu";
28 			operating-points = <
37 			clock-latency = <100000>;
41 			compatible = "arm,cortex-a9";
43 			reg = <0x901>;
44 			next-level-cache = <&L2>;
46 			clock-names = "cpu";
47 			operating-points = <
56 			clock-latency = <100000>;
60 			compatible = "arm,cortex-a9";
62 			reg = <0x902>;
63 			next-level-cache = <&L2>;
65 			clock-names = "cpu";
66 			operating-points = <
75 			clock-latency = <100000>;
79 			compatible = "arm,cortex-a9";
81 			reg = <0x903>;
82 			next-level-cache = <&L2>;
84 			clock-names = "cpu";
85 			operating-points = <
94 			clock-latency = <100000>;
101 		reg = <0x00000000 0xff900000>;
107 		memory-controller@fff00000 {
108 			compatible = "calxeda,hb-ddr-ctrl";
109 			reg = <0xfff00000 0x1000>;
114 			compatible = "arm,cortex-a9-twd-timer";
115 			reg = <0xfff10600 0x20>;
121 			compatible = "arm,cortex-a9-twd-wdt";
122 			reg = <0xfff10620 0x20>;
127 		intc: interrupt-controller@fff11000 {
128 			compatible = "arm,cortex-a9-gic";
129 			#interrupt-cells = <3>;
130 			interrupt-controller;
131 			reg = <0xfff11000 0x1000>,
135 		L2: cache-controller {
136 			compatible = "arm,pl310-cache";
137 			reg = <0xfff12000 0x1000>;
139 			cache-unified;
140 			cache-level = <2>;
144 			compatible = "arm,cortex-a9-pmu";
150 			compatible = "calxeda,hb-sregs-l2-ecc";
151 			reg = <0xfff3c200 0x100>;
158 /include/ "ecx-common.dtsi"