Lines Matching +full:clock +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
17 #include <dt-bindings/clock/exynos5250.h>
19 #include "exynos4-cpu-thermal.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
50 #address-cells = <1>;
51 #size-cells = <0>;
55 compatible = "arm,cortex-a15";
57 clocks = <&clock CLK_ARM_CLK>;
58 clock-names = "cpu";
59 operating-points-v2 = <&cpu0_opp_table>;
60 #cooling-cells = <2>; /* min followed by max */
64 compatible = "arm,cortex-a15";
66 clocks = <&clock CLK_ARM_CLK>;
67 clock-names = "cpu";
68 operating-points-v2 = <&cpu0_opp_table>;
69 #cooling-cells = <2>; /* min followed by max */
74 compatible = "operating-points-v2";
75 opp-shared;
77 opp-200000000 {
78 opp-hz = /bits/ 64 <200000000>;
79 opp-microvolt = <925000>;
80 clock-latency-ns = <140000>;
82 opp-300000000 {
83 opp-hz = /bits/ 64 <300000000>;
84 opp-microvolt = <937500>;
85 clock-latency-ns = <140000>;
87 opp-400000000 {
88 opp-hz = /bits/ 64 <400000000>;
89 opp-microvolt = <950000>;
90 clock-latency-ns = <140000>;
92 opp-500000000 {
93 opp-hz = /bits/ 64 <500000000>;
94 opp-microvolt = <975000>;
95 clock-latency-ns = <140000>;
97 opp-600000000 {
98 opp-hz = /bits/ 64 <600000000>;
99 opp-microvolt = <1000000>;
100 clock-latency-ns = <140000>;
102 opp-700000000 {
103 opp-hz = /bits/ 64 <700000000>;
104 opp-microvolt = <1012500>;
105 clock-latency-ns = <140000>;
107 opp-800000000 {
108 opp-hz = /bits/ 64 <800000000>;
109 opp-microvolt = <1025000>;
110 clock-latency-ns = <140000>;
112 opp-900000000 {
113 opp-hz = /bits/ 64 <900000000>;
114 opp-microvolt = <1050000>;
115 clock-latency-ns = <140000>;
117 opp-1000000000 {
118 opp-hz = /bits/ 64 <1000000000>;
119 opp-microvolt = <1075000>;
120 clock-latency-ns = <140000>;
121 opp-suspend;
123 opp-1100000000 {
124 opp-hz = /bits/ 64 <1100000000>;
125 opp-microvolt = <1100000>;
126 clock-latency-ns = <140000>;
128 opp-1200000000 {
129 opp-hz = /bits/ 64 <1200000000>;
130 opp-microvolt = <1125000>;
131 clock-latency-ns = <140000>;
133 opp-1300000000 {
134 opp-hz = /bits/ 64 <1300000000>;
135 opp-microvolt = <1150000>;
136 clock-latency-ns = <140000>;
138 opp-1400000000 {
139 opp-hz = /bits/ 64 <1400000000>;
140 opp-microvolt = <1200000>;
141 clock-latency-ns = <140000>;
143 opp-1500000000 {
144 opp-hz = /bits/ 64 <1500000000>;
145 opp-microvolt = <1225000>;
146 clock-latency-ns = <140000>;
148 opp-1600000000 {
149 opp-hz = /bits/ 64 <1600000000>;
150 opp-microvolt = <1250000>;
151 clock-latency-ns = <140000>;
153 opp-1700000000 {
154 opp-hz = /bits/ 64 <1700000000>;
155 opp-microvolt = <1300000>;
156 clock-latency-ns = <140000>;
161 compatible = "arm,cortex-a15-pmu";
162 interrupt-parent = <&combiner>;
168 compatible = "mmio-sram";
170 #address-cells = <1>;
171 #size-cells = <1>;
174 smp-sram@0 {
175 compatible = "samsung,exynos4210-sysram";
179 smp-sram@2f000 {
180 compatible = "samsung,exynos4210-sysram-ns";
185 pd_gsc: power-domain@10044000 {
186 compatible = "samsung,exynos4210-pd";
188 #power-domain-cells = <0>;
192 pd_mfc: power-domain@10044040 {
193 compatible = "samsung,exynos4210-pd";
195 #power-domain-cells = <0>;
199 pd_g3d: power-domain@10044060 {
200 compatible = "samsung,exynos4210-pd";
202 #power-domain-cells = <0>;
206 pd_disp1: power-domain@100440a0 {
207 compatible = "samsung,exynos4210-pd";
209 #power-domain-cells = <0>;
213 pd_mau: power-domain@100440c0 {
214 compatible = "samsung,exynos4210-pd";
216 #power-domain-cells = <0>;
220 clock: clock-controller@10010000 { label
221 compatible = "samsung,exynos5250-clock";
223 #clock-cells = <1>;
226 clock_audss: audss-clock-controller@3810000 {
227 compatible = "samsung,exynos5250-audss-clock";
229 #clock-cells = <1>;
230 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
231 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
232 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
233 power-domains = <&pd_mau>;
237 compatible = "samsung,exynos4210-mct";
239 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
240 clock-names = "fin_pll", "mct";
241 interrupts-extended = <&combiner 23 3>,
250 compatible = "samsung,exynos5250-pinctrl";
254 wakup_eint: wakeup-interrupt-controller {
255 compatible = "samsung,exynos4210-wakeup-eint";
256 interrupt-parent = <&gic>;
262 compatible = "samsung,exynos5250-pinctrl";
268 compatible = "samsung,exynos5250-pinctrl";
274 compatible = "samsung,exynos5250-pinctrl";
277 power-domains = <&pd_mau>;
280 pmu_system_controller: system-controller@10040000 {
281 compatible = "samsung,exynos5250-pmu", "syscon";
283 clock-names = "clkout16";
284 clocks = <&clock CLK_FIN_PLL>;
285 #clock-cells = <1>;
286 interrupt-controller;
287 #interrupt-cells = <3>;
288 interrupt-parent = <&gic>;
292 compatible = "samsung,exynos5250-wdt";
295 clocks = <&clock CLK_WDT>;
296 clock-names = "watchdog";
297 samsung,syscon-phandle = <&pmu_system_controller>;
301 compatible = "samsung,mfc-v6";
304 power-domains = <&pd_mfc>;
305 clocks = <&clock CLK_MFC>;
306 clock-names = "mfc";
308 iommu-names = "left", "right";
312 compatible = "samsung,exynos5250-rotator";
315 clocks = <&clock CLK_ROTATOR>;
316 clock-names = "rotator";
321 compatible = "samsung,exynos5250-mali", "arm,mali-t604";
326 interrupt-names = "job", "mmu", "gpu";
327 clocks = <&clock CLK_G3D>;
328 clock-names = "core";
329 operating-points-v2 = <&gpu_opp_table>;
330 power-domains = <&pd_g3d>;
333 gpu_opp_table: opp-table {
334 compatible = "operating-points-v2";
336 opp-100000000 {
337 opp-hz = /bits/ 64 <100000000>;
338 opp-microvolt = <925000>;
340 opp-160000000 {
341 opp-hz = /bits/ 64 <160000000>;
342 opp-microvolt = <925000>;
344 opp-266000000 {
345 opp-hz = /bits/ 64 <266000000>;
346 opp-microvolt = <1025000>;
348 opp-350000000 {
349 opp-hz = /bits/ 64 <350000000>;
350 opp-microvolt = <1075000>;
352 opp-400000000 {
353 opp-hz = /bits/ 64 <400000000>;
354 opp-microvolt = <1125000>;
356 opp-450000000 {
357 opp-hz = /bits/ 64 <450000000>;
358 opp-microvolt = <1150000>;
360 opp-533000000 {
361 opp-hz = /bits/ 64 <533000000>;
362 opp-microvolt = <1250000>;
368 compatible = "samsung,exynos5250-tmu";
371 clocks = <&clock CLK_TMU>;
372 clock-names = "tmu_apbif";
373 #thermal-sensor-cells = <0>;
377 compatible = "snps,dwc-ahci";
378 samsung,sata-freq = <66>;
381 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
382 clock-names = "sata", "sclk_sata";
384 phy-names = "sata-phy";
385 ports-implemented = <0x1>;
389 sata_phy: sata-phy@12170000 {
390 compatible = "samsung,exynos5250-sata-phy";
392 clocks = <&clock CLK_SATA_PHYCTRL>;
393 clock-names = "sata_phyctrl";
394 #phy-cells = <0>;
395 samsung,syscon-phandle = <&pmu_system_controller>;
399 /* i2c_0-3 are defined in exynos5.dtsi */
401 compatible = "samsung,s3c2440-i2c";
404 #address-cells = <1>;
405 #size-cells = <0>;
406 clocks = <&clock CLK_I2C4>;
407 clock-names = "i2c";
408 pinctrl-names = "default";
409 pinctrl-0 = <&i2c4_bus>;
414 compatible = "samsung,s3c2440-i2c";
417 #address-cells = <1>;
418 #size-cells = <0>;
419 clocks = <&clock CLK_I2C5>;
420 clock-names = "i2c";
421 pinctrl-names = "default";
422 pinctrl-0 = <&i2c5_bus>;
427 compatible = "samsung,s3c2440-i2c";
430 #address-cells = <1>;
431 #size-cells = <0>;
432 clocks = <&clock CLK_I2C6>;
433 clock-names = "i2c";
434 pinctrl-names = "default";
435 pinctrl-0 = <&i2c6_bus>;
440 compatible = "samsung,s3c2440-i2c";
443 #address-cells = <1>;
444 #size-cells = <0>;
445 clocks = <&clock CLK_I2C7>;
446 clock-names = "i2c";
447 pinctrl-names = "default";
448 pinctrl-0 = <&i2c7_bus>;
453 compatible = "samsung,s3c2440-hdmiphy-i2c";
456 #address-cells = <1>;
457 #size-cells = <0>;
458 clocks = <&clock CLK_I2C_HDMI>;
459 clock-names = "i2c";
463 compatible = "samsung,exynos4212-hdmiphy";
469 compatible = "samsung,exynos5-sata-phy-i2c";
471 #address-cells = <1>;
472 #size-cells = <0>;
473 clocks = <&clock CLK_SATA_PHYI2C>;
474 clock-names = "i2c";
477 sata_phy_i2c: sata-phy-i2c@38 {
478 compatible = "samsung,exynos-sataphy-i2c";
485 compatible = "samsung,exynos4210-spi";
491 dma-names = "tx", "rx";
492 #address-cells = <1>;
493 #size-cells = <0>;
494 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
495 clock-names = "spi", "spi_busclk0";
496 pinctrl-names = "default";
497 pinctrl-0 = <&spi0_bus>;
501 compatible = "samsung,exynos4210-spi";
507 dma-names = "tx", "rx";
508 #address-cells = <1>;
509 #size-cells = <0>;
510 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
511 clock-names = "spi", "spi_busclk0";
512 pinctrl-names = "default";
513 pinctrl-0 = <&spi1_bus>;
517 compatible = "samsung,exynos4210-spi";
523 dma-names = "tx", "rx";
524 #address-cells = <1>;
525 #size-cells = <0>;
526 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
527 clock-names = "spi", "spi_busclk0";
528 pinctrl-names = "default";
529 pinctrl-0 = <&spi2_bus>;
533 compatible = "samsung,exynos5250-dw-mshc";
535 #address-cells = <1>;
536 #size-cells = <0>;
538 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
539 clock-names = "biu", "ciu";
540 fifo-depth = <0x80>;
545 compatible = "samsung,exynos5250-dw-mshc";
547 #address-cells = <1>;
548 #size-cells = <0>;
550 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
551 clock-names = "biu", "ciu";
552 fifo-depth = <0x80>;
557 compatible = "samsung,exynos5250-dw-mshc";
559 #address-cells = <1>;
560 #size-cells = <0>;
562 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
563 clock-names = "biu", "ciu";
564 fifo-depth = <0x80>;
569 compatible = "samsung,exynos5250-dw-mshc";
572 #address-cells = <1>;
573 #size-cells = <0>;
574 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
575 clock-names = "biu", "ciu";
576 fifo-depth = <0x80>;
581 compatible = "samsung,s5pv210-i2s";
587 dma-names = "tx", "rx", "tx-sec";
591 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
592 samsung,idma-addr = <0x03000000>;
593 pinctrl-names = "default";
594 pinctrl-0 = <&i2s0_bus>;
595 power-domains = <&pd_mau>;
596 #clock-cells = <1>;
597 #sound-dai-cells = <1>;
601 compatible = "samsung,s3c6410-i2s";
606 dma-names = "tx", "rx";
607 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
608 clock-names = "iis", "i2s_opclk0";
609 pinctrl-names = "default";
610 pinctrl-0 = <&i2s1_bus>;
611 power-domains = <&pd_mau>;
612 #sound-dai-cells = <1>;
616 compatible = "samsung,s3c6410-i2s";
621 dma-names = "tx", "rx";
622 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
623 clock-names = "iis", "i2s_opclk0";
624 pinctrl-names = "default";
625 pinctrl-0 = <&i2s2_bus>;
626 power-domains = <&pd_mau>;
627 #sound-dai-cells = <1>;
631 compatible = "samsung,exynos5250-dwusb3";
632 clocks = <&clock CLK_USB3>;
633 clock-names = "usbdrd30";
634 #address-cells = <1>;
635 #size-cells = <1>;
643 phy-names = "usb2-phy", "usb3-phy";
648 compatible = "samsung,exynos5250-usbdrd-phy";
650 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
651 clock-names = "phy", "ref";
652 samsung,pmu-syscon = <&pmu_system_controller>;
653 #phy-cells = <1>;
657 compatible = "samsung,exynos4210-ehci";
661 clocks = <&clock CLK_USB2>;
662 clock-names = "usbhost";
664 phy-names = "host";
668 compatible = "samsung,exynos4210-ohci";
672 clocks = <&clock CLK_USB2>;
673 clock-names = "usbhost";
675 phy-names = "host";
679 compatible = "samsung,exynos5250-usb2-phy";
681 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
682 clock-names = "phy", "ref";
683 #phy-cells = <1>;
684 samsung,sysreg-phandle = <&sysreg_system_controller>;
685 samsung,pmureg-phandle = <&pmu_system_controller>;
692 clocks = <&clock CLK_PDMA0>;
693 clock-names = "apb_pclk";
694 #dma-cells = <1>;
695 #dma-channels = <8>;
696 #dma-requests = <32>;
703 clocks = <&clock CLK_PDMA1>;
704 clock-names = "apb_pclk";
705 #dma-cells = <1>;
706 #dma-channels = <8>;
707 #dma-requests = <32>;
714 clocks = <&clock CLK_MDMA0>;
715 clock-names = "apb_pclk";
716 #dma-cells = <1>;
717 #dma-channels = <8>;
718 #dma-requests = <1>;
725 clocks = <&clock CLK_MDMA1>;
726 clock-names = "apb_pclk";
727 #dma-cells = <1>;
728 #dma-channels = <8>;
729 #dma-requests = <1>;
733 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
736 power-domains = <&pd_gsc>;
737 clocks = <&clock CLK_GSCL0>;
738 clock-names = "gscl";
743 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
746 power-domains = <&pd_gsc>;
747 clocks = <&clock CLK_GSCL1>;
748 clock-names = "gscl";
753 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
756 power-domains = <&pd_gsc>;
757 clocks = <&clock CLK_GSCL2>;
758 clock-names = "gscl";
763 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
766 power-domains = <&pd_gsc>;
767 clocks = <&clock CLK_GSCL3>;
768 clock-names = "gscl";
773 compatible = "samsung,exynos4212-hdmi";
775 power-domains = <&pd_disp1>;
777 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
778 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
779 <&clock CLK_MOUT_HDMI>;
780 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
782 samsung,syscon-phandle = <&pmu_system_controller>;
784 #sound-dai-cells = <0>;
789 compatible = "samsung,s5p-cec";
792 clocks = <&clock CLK_HDMI_CEC>;
793 clock-names = "hdmicec";
794 samsung,syscon-phandle = <&pmu_system_controller>;
795 hdmi-phandle = <&hdmi>;
796 pinctrl-names = "default";
797 pinctrl-0 = <&hdmi_cec>;
802 compatible = "samsung,exynos5250-mixer";
804 power-domains = <&pd_disp1>;
806 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
807 <&clock CLK_SCLK_HDMI>;
808 clock-names = "mixer", "hdmi", "sclk_hdmi";
813 dp_phy: video-phy {
814 compatible = "samsung,exynos5250-dp-video-phy";
815 samsung,pmu-syscon = <&pmu_system_controller>;
816 #phy-cells = <0>;
819 mipi_phy: video-phy@10040710 {
820 compatible = "samsung,s5pv210-mipi-video-phy";
822 #phy-cells = <1>;
827 compatible = "samsung,exynos4210-mipi-dsi";
830 samsung,power-domain = <&pd_disp1>;
832 phy-names = "dsim";
833 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>;
834 clock-names = "bus_clk", "sclk_mipi";
836 #address-cells = <1>;
837 #size-cells = <0>;
841 compatible = "samsung,exynos-adc-v1";
844 clocks = <&clock CLK_ADC>;
845 clock-names = "adc";
846 #io-channel-cells = <1>;
847 io-channel-ranges;
848 samsung,syscon-phandle = <&pmu_system_controller>;
853 compatible = "samsung,exynos-sysmmu";
855 interrupt-parent = <&combiner>;
857 clock-names = "sysmmu", "master";
858 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
859 #iommu-cells = <0>;
863 compatible = "samsung,exynos-sysmmu";
865 interrupt-parent = <&combiner>;
867 power-domains = <&pd_mfc>;
868 clock-names = "sysmmu", "master";
869 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
870 #iommu-cells = <0>;
874 compatible = "samsung,exynos-sysmmu";
876 interrupt-parent = <&combiner>;
878 power-domains = <&pd_mfc>;
879 clock-names = "sysmmu", "master";
880 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
881 #iommu-cells = <0>;
885 compatible = "samsung,exynos-sysmmu";
887 interrupt-parent = <&combiner>;
889 clock-names = "sysmmu", "master";
890 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
891 #iommu-cells = <0>;
895 compatible = "samsung,exynos-sysmmu";
897 interrupt-parent = <&combiner>;
899 power-domains = <&pd_gsc>;
900 clock-names = "sysmmu", "master";
901 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
902 #iommu-cells = <0>;
906 compatible = "samsung,exynos-sysmmu";
908 interrupt-parent = <&combiner>;
910 clock-names = "sysmmu";
911 clocks = <&clock CLK_SMMU_FIMC_ISP>;
912 #iommu-cells = <0>;
916 compatible = "samsung,exynos-sysmmu";
918 interrupt-parent = <&combiner>;
920 clock-names = "sysmmu";
921 clocks = <&clock CLK_SMMU_FIMC_DRC>;
922 #iommu-cells = <0>;
926 compatible = "samsung,exynos-sysmmu";
928 interrupt-parent = <&combiner>;
930 clock-names = "sysmmu";
931 clocks = <&clock CLK_SMMU_FIMC_FD>;
932 #iommu-cells = <0>;
936 compatible = "samsung,exynos-sysmmu";
938 interrupt-parent = <&combiner>;
940 clock-names = "sysmmu";
941 clocks = <&clock CLK_SMMU_FIMC_SCC>;
942 #iommu-cells = <0>;
946 compatible = "samsung,exynos-sysmmu";
948 interrupt-parent = <&combiner>;
950 clock-names = "sysmmu";
951 clocks = <&clock CLK_SMMU_FIMC_SCP>;
952 #iommu-cells = <0>;
956 compatible = "samsung,exynos-sysmmu";
958 interrupt-parent = <&combiner>;
960 clock-names = "sysmmu";
961 clocks = <&clock CLK_SMMU_FIMC_MCU>;
962 #iommu-cells = <0>;
966 compatible = "samsung,exynos-sysmmu";
968 interrupt-parent = <&combiner>;
970 clock-names = "sysmmu";
971 clocks = <&clock CLK_SMMU_FIMC_ODC>;
972 #iommu-cells = <0>;
976 compatible = "samsung,exynos-sysmmu";
978 interrupt-parent = <&combiner>;
980 clock-names = "sysmmu";
981 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
982 #iommu-cells = <0>;
986 compatible = "samsung,exynos-sysmmu";
988 interrupt-parent = <&combiner>;
990 clock-names = "sysmmu";
991 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
992 #iommu-cells = <0>;
996 compatible = "samsung,exynos-sysmmu";
998 interrupt-parent = <&combiner>;
1000 clock-names = "sysmmu";
1001 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
1002 #iommu-cells = <0>;
1006 compatible = "samsung,exynos-sysmmu";
1008 interrupt-parent = <&combiner>;
1010 power-domains = <&pd_gsc>;
1011 clock-names = "sysmmu", "master";
1012 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
1013 #iommu-cells = <0>;
1017 compatible = "samsung,exynos-sysmmu";
1019 interrupt-parent = <&combiner>;
1021 power-domains = <&pd_gsc>;
1022 clock-names = "sysmmu", "master";
1023 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
1024 #iommu-cells = <0>;
1028 compatible = "samsung,exynos-sysmmu";
1030 interrupt-parent = <&combiner>;
1032 power-domains = <&pd_gsc>;
1033 clock-names = "sysmmu", "master";
1034 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1035 #iommu-cells = <0>;
1039 compatible = "samsung,exynos-sysmmu";
1041 interrupt-parent = <&combiner>;
1043 power-domains = <&pd_gsc>;
1044 clock-names = "sysmmu", "master";
1045 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1046 #iommu-cells = <0>;
1050 compatible = "samsung,exynos-sysmmu";
1052 interrupt-parent = <&combiner>;
1054 power-domains = <&pd_gsc>;
1055 clock-names = "sysmmu", "master";
1056 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
1057 #iommu-cells = <0>;
1061 compatible = "samsung,exynos-sysmmu";
1063 interrupt-parent = <&combiner>;
1065 power-domains = <&pd_gsc>;
1066 clock-names = "sysmmu", "master";
1067 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
1068 #iommu-cells = <0>;
1072 compatible = "samsung,exynos-sysmmu";
1074 interrupt-parent = <&combiner>;
1076 power-domains = <&pd_disp1>;
1077 clock-names = "sysmmu", "master";
1078 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
1079 #iommu-cells = <0>;
1083 compatible = "samsung,exynos-sysmmu";
1085 interrupt-parent = <&combiner>;
1087 power-domains = <&pd_disp1>;
1088 clock-names = "sysmmu", "master";
1089 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
1090 #iommu-cells = <0>;
1095 compatible = "arm,armv7-timer";
1102 * of U-Boot on Exynos don't set the CNTFRQ register,
1105 clock-frequency = <24000000>;
1110 polling-delay-passive = <0>;
1111 polling-delay = <0>;
1112 thermal-sensors = <&tmu 0>;
1114 cooling-maps {
1117 cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
1121 cooling-device = <&cpu0 15 15>,
1128 power-domains = <&pd_disp1>;
1129 clocks = <&clock CLK_DP>;
1130 clock-names = "dp";
1132 phy-names = "dp";
1136 power-domains = <&pd_disp1>;
1137 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1138 clock-names = "sclk_fimd", "fimd";
1144 clocks = <&clock CLK_G2D>;
1145 clock-names = "fimg2d";
1150 clocks = <&clock CLK_I2C0>;
1151 clock-names = "i2c";
1152 pinctrl-names = "default";
1153 pinctrl-0 = <&i2c0_bus>;
1157 clocks = <&clock CLK_I2C1>;
1158 clock-names = "i2c";
1159 pinctrl-names = "default";
1160 pinctrl-0 = <&i2c1_bus>;
1164 clocks = <&clock CLK_I2C2>;
1165 clock-names = "i2c";
1166 pinctrl-names = "default";
1167 pinctrl-0 = <&i2c2_bus>;
1171 clocks = <&clock CLK_I2C3>;
1172 clock-names = "i2c";
1173 pinctrl-names = "default";
1174 pinctrl-0 = <&i2c3_bus>;
1178 clocks = <&clock CLK_SSS>;
1179 clock-names = "secss";
1183 clocks = <&clock CLK_PWM>;
1184 clock-names = "timers";
1188 clocks = <&clock CLK_RTC>;
1189 clock-names = "rtc";
1190 interrupt-parent = <&pmu_system_controller>;
1195 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1196 clock-names = "uart", "clk_uart_baud0";
1198 dma-names = "rx", "tx";
1202 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1203 clock-names = "uart", "clk_uart_baud0";
1205 dma-names = "rx", "tx";
1209 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1210 clock-names = "uart", "clk_uart_baud0";
1212 dma-names = "rx", "tx";
1216 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1217 clock-names = "uart", "clk_uart_baud0";
1219 dma-names = "rx", "tx";
1223 clocks = <&clock CLK_SSS>;
1224 clock-names = "secss";
1228 clocks = <&clock CLK_SSS>;
1229 clock-names = "secss";
1232 #include "exynos5250-pinctrl.dtsi"
1233 #include "exynos-syscon-restart.dtsi"