Lines Matching +full:clock +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
19 #include <dt-bindings/clock/exynos4.h>
20 #include <dt-bindings/clock/exynos-audss-clk.h>
21 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/interrupt-controller/irq.h>
25 interrupt-parent = <&gic>;
26 #address-cells = <1>;
27 #size-cells = <1>;
55 compatible = "arm,cortex-a9-pmu";
56 interrupt-parent = <&combiner>;
61 compatible = "simple-bus";
62 #address-cells = <1>;
63 #size-cells = <1>;
66 clock_audss: clock-controller@3810000 {
67 compatible = "samsung,exynos4210-audss-clock";
69 #clock-cells = <1>;
70 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
71 <&clock CLK_SCLK_AUDIO0>,
72 <&clock CLK_SCLK_AUDIO0>;
73 clock-names = "pll_ref", "pll_in", "sclk_audio",
78 compatible = "samsung,s5pv210-i2s";
83 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
84 #clock-cells = <1>;
85 clock-output-names = "i2s_cdclk0";
87 dma-names = "tx", "rx", "tx-sec";
88 samsung,idma-addr = <0x03000000>;
89 #sound-dai-cells = <1>;
94 compatible = "samsung,exynos4210-chipid";
98 scu: snoop-control-unit@10500000 {
99 compatible = "arm,cortex-a9-scu";
103 memory-controller@12570000 {
104 compatible = "samsung,exynos4210-srom";
108 mipi_phy: video-phy {
109 compatible = "samsung,s5pv210-mipi-video-phy";
110 #phy-cells = <1>;
114 pd_mfc: power-domain@10023c40 {
115 compatible = "samsung,exynos4210-pd";
117 #power-domain-cells = <0>;
121 pd_g3d: power-domain@10023c60 {
122 compatible = "samsung,exynos4210-pd";
124 #power-domain-cells = <0>;
128 pd_lcd0: power-domain@10023c80 {
129 compatible = "samsung,exynos4210-pd";
131 #power-domain-cells = <0>;
135 pd_tv: power-domain@10023c20 {
136 compatible = "samsung,exynos4210-pd";
138 #power-domain-cells = <0>;
139 power-domains = <&pd_lcd0>;
143 pd_cam: power-domain@10023c00 {
144 compatible = "samsung,exynos4210-pd";
146 #power-domain-cells = <0>;
150 pd_gps: power-domain@10023ce0 {
151 compatible = "samsung,exynos4210-pd";
153 #power-domain-cells = <0>;
157 pd_gps_alive: power-domain@10023d00 {
158 compatible = "samsung,exynos4210-pd";
160 #power-domain-cells = <0>;
164 gic: interrupt-controller@10490000 {
165 compatible = "arm,cortex-a9-gic";
166 #interrupt-cells = <3>;
167 interrupt-controller;
171 combiner: interrupt-controller@10440000 {
172 compatible = "samsung,exynos4210-combiner";
173 #interrupt-cells = <2>;
174 interrupt-controller;
179 compatible = "samsung,exynos4-sysreg", "syscon";
183 pmu_system_controller: system-controller@10020000 {
184 compatible = "samsung,exynos4210-pmu", "syscon";
186 interrupt-controller;
187 #interrupt-cells = <3>;
188 interrupt-parent = <&gic>;
192 compatible = "samsung,exynos4210-mipi-dsi";
195 power-domains = <&pd_lcd0>;
197 phy-names = "dsim";
198 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
199 clock-names = "bus_clk", "sclk_mipi";
201 #address-cells = <1>;
202 #size-cells = <0>;
206 compatible = "samsung,fimc", "simple-bus";
208 #address-cells = <1>;
209 #size-cells = <1>;
210 #clock-cells = <1>;
211 clock-output-names = "cam_a_clkout", "cam_b_clkout";
215 compatible = "samsung,exynos4210-fimc";
218 clocks = <&clock CLK_FIMC0>,
219 <&clock CLK_SCLK_FIMC0>;
220 clock-names = "fimc", "sclk_fimc";
221 power-domains = <&pd_cam>;
228 compatible = "samsung,exynos4210-fimc";
231 clocks = <&clock CLK_FIMC1>,
232 <&clock CLK_SCLK_FIMC1>;
233 clock-names = "fimc", "sclk_fimc";
234 power-domains = <&pd_cam>;
241 compatible = "samsung,exynos4210-fimc";
244 clocks = <&clock CLK_FIMC2>,
245 <&clock CLK_SCLK_FIMC2>;
246 clock-names = "fimc", "sclk_fimc";
247 power-domains = <&pd_cam>;
254 compatible = "samsung,exynos4210-fimc";
257 clocks = <&clock CLK_FIMC3>,
258 <&clock CLK_SCLK_FIMC3>;
259 clock-names = "fimc", "sclk_fimc";
260 power-domains = <&pd_cam>;
267 compatible = "samsung,exynos4210-csis";
270 clocks = <&clock CLK_CSIS0>,
271 <&clock CLK_SCLK_CSIS0>;
272 clock-names = "csis", "sclk_csis";
273 bus-width = <4>;
274 power-domains = <&pd_cam>;
276 phy-names = "csis";
278 #address-cells = <1>;
279 #size-cells = <0>;
283 compatible = "samsung,exynos4210-csis";
286 clocks = <&clock CLK_CSIS1>,
287 <&clock CLK_SCLK_CSIS1>;
288 clock-names = "csis", "sclk_csis";
289 bus-width = <2>;
290 power-domains = <&pd_cam>;
292 phy-names = "csis";
294 #address-cells = <1>;
295 #size-cells = <0>;
300 compatible = "samsung,s3c6410-rtc";
302 interrupt-parent = <&pmu_system_controller>;
305 clocks = <&clock CLK_RTC>;
306 clock-names = "rtc";
311 compatible = "samsung,s5pv210-keypad";
314 clocks = <&clock CLK_KEYIF>;
315 clock-names = "keypad";
320 compatible = "samsung,exynos4210-sdhci";
323 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
324 clock-names = "hsmmc", "mmc_busclk.2";
329 compatible = "samsung,exynos4210-sdhci";
332 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
333 clock-names = "hsmmc", "mmc_busclk.2";
338 compatible = "samsung,exynos4210-sdhci";
341 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
342 clock-names = "hsmmc", "mmc_busclk.2";
347 compatible = "samsung,exynos4210-sdhci";
350 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
351 clock-names = "hsmmc", "mmc_busclk.2";
355 exynos_usbphy: exynos-usbphy@125b0000 {
356 compatible = "samsung,exynos4210-usb2-phy";
358 samsung,pmureg-phandle = <&pmu_system_controller>;
359 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
360 clock-names = "phy", "ref";
361 #phy-cells = <1>;
366 compatible = "samsung,s3c6400-hsotg";
369 clocks = <&clock CLK_USB_DEVICE>;
370 clock-names = "otg";
372 phy-names = "usb2-phy";
377 compatible = "samsung,exynos4210-ehci";
380 clocks = <&clock CLK_USB_HOST>;
381 clock-names = "usbhost";
384 phy-names = "host", "hsic0", "hsic1";
388 compatible = "samsung,exynos4210-ohci";
391 clocks = <&clock CLK_USB_HOST>;
392 clock-names = "usbhost";
395 phy-names = "host";
399 compatible = "samsung,exynos4210-mali", "arm,mali-400";
402 * CLK_G3D is not actually bus clock but a IP-level clock.
403 * The bus clock is not described in hardware manual.
405 clocks = <&clock CLK_G3D>,
406 <&clock CLK_SCLK_G3D>;
407 clock-names = "bus", "core";
408 power-domains = <&pd_g3d>;
413 compatible = "samsung,s3c6410-i2s";
415 clocks = <&clock CLK_I2S1>;
416 clock-names = "iis";
417 #clock-cells = <1>;
418 clock-output-names = "i2s_cdclk1";
420 dma-names = "tx", "rx";
421 #sound-dai-cells = <1>;
426 compatible = "samsung,s3c6410-i2s";
428 clocks = <&clock CLK_I2S2>;
429 clock-names = "iis";
430 #clock-cells = <1>;
431 clock-output-names = "i2s_cdclk2";
433 dma-names = "tx", "rx";
434 #sound-dai-cells = <1>;
439 compatible = "samsung,mfc-v5";
442 power-domains = <&pd_mfc>;
443 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
444 clock-names = "mfc", "sclk_mfc";
446 iommu-names = "left", "right";
450 compatible = "samsung,exynos4210-uart";
453 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
454 clock-names = "uart", "clk_uart_baud0";
456 dma-names = "rx", "tx";
461 compatible = "samsung,exynos4210-uart";
464 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
465 clock-names = "uart", "clk_uart_baud0";
467 dma-names = "rx", "tx";
472 compatible = "samsung,exynos4210-uart";
475 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
476 clock-names = "uart", "clk_uart_baud0";
478 dma-names = "rx", "tx";
483 compatible = "samsung,exynos4210-uart";
486 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
487 clock-names = "uart", "clk_uart_baud0";
489 dma-names = "rx", "tx";
494 #address-cells = <1>;
495 #size-cells = <0>;
496 compatible = "samsung,s3c2440-i2c";
499 clocks = <&clock CLK_I2C0>;
500 clock-names = "i2c";
501 pinctrl-names = "default";
502 pinctrl-0 = <&i2c0_bus>;
507 #address-cells = <1>;
508 #size-cells = <0>;
509 compatible = "samsung,s3c2440-i2c";
512 clocks = <&clock CLK_I2C1>;
513 clock-names = "i2c";
514 pinctrl-names = "default";
515 pinctrl-0 = <&i2c1_bus>;
520 #address-cells = <1>;
521 #size-cells = <0>;
522 compatible = "samsung,s3c2440-i2c";
525 clocks = <&clock CLK_I2C2>;
526 clock-names = "i2c";
527 pinctrl-names = "default";
528 pinctrl-0 = <&i2c2_bus>;
533 #address-cells = <1>;
534 #size-cells = <0>;
535 compatible = "samsung,s3c2440-i2c";
538 clocks = <&clock CLK_I2C3>;
539 clock-names = "i2c";
540 pinctrl-names = "default";
541 pinctrl-0 = <&i2c3_bus>;
546 #address-cells = <1>;
547 #size-cells = <0>;
548 compatible = "samsung,s3c2440-i2c";
551 clocks = <&clock CLK_I2C4>;
552 clock-names = "i2c";
553 pinctrl-names = "default";
554 pinctrl-0 = <&i2c4_bus>;
559 #address-cells = <1>;
560 #size-cells = <0>;
561 compatible = "samsung,s3c2440-i2c";
564 clocks = <&clock CLK_I2C5>;
565 clock-names = "i2c";
566 pinctrl-names = "default";
567 pinctrl-0 = <&i2c5_bus>;
572 #address-cells = <1>;
573 #size-cells = <0>;
574 compatible = "samsung,s3c2440-i2c";
577 clocks = <&clock CLK_I2C6>;
578 clock-names = "i2c";
579 pinctrl-names = "default";
580 pinctrl-0 = <&i2c6_bus>;
585 #address-cells = <1>;
586 #size-cells = <0>;
587 compatible = "samsung,s3c2440-i2c";
590 clocks = <&clock CLK_I2C7>;
591 clock-names = "i2c";
592 pinctrl-names = "default";
593 pinctrl-0 = <&i2c7_bus>;
598 #address-cells = <1>;
599 #size-cells = <0>;
600 compatible = "samsung,s3c2440-hdmiphy-i2c";
603 clocks = <&clock CLK_I2C_HDMI>;
604 clock-names = "i2c";
608 compatible = "exynos4210-hdmiphy";
614 compatible = "samsung,exynos4210-spi";
618 dma-names = "tx", "rx";
619 #address-cells = <1>;
620 #size-cells = <0>;
621 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
622 clock-names = "spi", "spi_busclk0";
623 pinctrl-names = "default";
624 pinctrl-0 = <&spi0_bus>;
629 compatible = "samsung,exynos4210-spi";
633 dma-names = "tx", "rx";
634 #address-cells = <1>;
635 #size-cells = <0>;
636 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
637 clock-names = "spi", "spi_busclk0";
638 pinctrl-names = "default";
639 pinctrl-0 = <&spi1_bus>;
644 compatible = "samsung,exynos4210-spi";
648 dma-names = "tx", "rx";
649 #address-cells = <1>;
650 #size-cells = <0>;
651 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
652 clock-names = "spi", "spi_busclk0";
653 pinctrl-names = "default";
654 pinctrl-0 = <&spi2_bus>;
659 compatible = "samsung,exynos4210-pwm";
666 clocks = <&clock CLK_PWM>;
667 clock-names = "timers";
668 #pwm-cells = <3>;
676 clocks = <&clock CLK_PDMA0>;
677 clock-names = "apb_pclk";
678 #dma-cells = <1>;
679 #dma-channels = <8>;
680 #dma-requests = <32>;
687 clocks = <&clock CLK_PDMA1>;
688 clock-names = "apb_pclk";
689 #dma-cells = <1>;
690 #dma-channels = <8>;
691 #dma-requests = <32>;
698 clocks = <&clock CLK_MDMA>;
699 clock-names = "apb_pclk";
700 #dma-cells = <1>;
701 #dma-channels = <8>;
702 #dma-requests = <1>;
706 compatible = "samsung,exynos4210-fimd";
707 interrupt-parent = <&combiner>;
709 interrupt-names = "fifo", "vsync", "lcd_sys";
711 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
712 clock-names = "sclk_fimd", "fimd";
713 power-domains = <&pd_lcd0>;
720 interrupt-parent = <&combiner>;
724 #thermal-sensor-cells = <0>;
727 jpeg_codec: jpeg-codec@11840000 {
728 compatible = "samsung,exynos4210-jpeg";
731 clocks = <&clock CLK_JPEG>;
732 clock-names = "jpeg";
733 power-domains = <&pd_cam>;
738 compatible = "samsung,exynos4210-rotator";
741 clocks = <&clock CLK_ROTATOR>;
742 clock-names = "rotator";
747 compatible = "samsung,exynos4210-hdmi";
750 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
752 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
753 <&clock CLK_SCLK_PIXEL>,
754 <&clock CLK_SCLK_HDMIPHY>,
755 <&clock CLK_MOUT_HDMI>;
757 power-domains = <&pd_tv>;
758 samsung,syscon-phandle = <&pmu_system_controller>;
759 #sound-dai-cells = <0>;
764 compatible = "samsung,s5p-cec";
767 clocks = <&clock CLK_HDMI_CEC>;
768 clock-names = "hdmicec";
769 samsung,syscon-phandle = <&pmu_system_controller>;
770 hdmi-phandle = <&hdmi>;
771 pinctrl-names = "default";
772 pinctrl-0 = <&hdmi_cec>;
777 compatible = "samsung,exynos4210-mixer";
780 power-domains = <&pd_tv>;
786 compatible = "samsung,exynos-ppmu";
788 clocks = <&clock CLK_PPMUDMC0>;
789 clock-names = "ppmu";
794 compatible = "samsung,exynos-ppmu";
796 clocks = <&clock CLK_PPMUDMC1>;
797 clock-names = "ppmu";
802 compatible = "samsung,exynos-ppmu";
804 clocks = <&clock CLK_PPMUCPU>;
805 clock-names = "ppmu";
810 compatible = "samsung,exynos-ppmu";
812 clocks = <&clock CLK_PPMURIGHT>;
813 clock-names = "ppmu";
818 compatible = "samsung,exynos-ppmu";
820 clocks = <&clock CLK_PPMULEFT>;
821 clock-names = "ppmu";
826 compatible = "samsung,exynos-ppmu";
828 clocks = <&clock CLK_PPMUCAMIF>;
829 clock-names = "ppmu";
834 compatible = "samsung,exynos-ppmu";
836 clocks = <&clock CLK_PPMULCD0>;
837 clock-names = "ppmu";
842 compatible = "samsung,exynos-ppmu";
848 compatible = "samsung,exynos-ppmu";
850 clocks = <&clock CLK_PPMUIMAGE>;
851 clock-names = "ppmu";
856 compatible = "samsung,exynos-ppmu";
858 clocks = <&clock CLK_PPMUTV>;
859 clock-names = "ppmu";
864 compatible = "samsung,exynos-ppmu";
866 clocks = <&clock CLK_PPMUG3D>;
867 clock-names = "ppmu";
872 compatible = "samsung,exynos-ppmu";
874 clocks = <&clock CLK_PPMUMFC_L>;
875 clock-names = "ppmu";
880 compatible = "samsung,exynos-ppmu";
882 clocks = <&clock CLK_PPMUMFC_R>;
883 clock-names = "ppmu";
888 compatible = "samsung,exynos-sysmmu";
890 interrupt-parent = <&combiner>;
892 clock-names = "sysmmu", "master";
893 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
894 power-domains = <&pd_mfc>;
895 #iommu-cells = <0>;
899 compatible = "samsung,exynos-sysmmu";
901 interrupt-parent = <&combiner>;
903 clock-names = "sysmmu", "master";
904 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
905 power-domains = <&pd_mfc>;
906 #iommu-cells = <0>;
910 compatible = "samsung,exynos-sysmmu";
912 interrupt-parent = <&combiner>;
914 clock-names = "sysmmu", "master";
915 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
916 power-domains = <&pd_tv>;
917 #iommu-cells = <0>;
921 compatible = "samsung,exynos-sysmmu";
923 interrupt-parent = <&combiner>;
925 clock-names = "sysmmu", "master";
926 clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
927 power-domains = <&pd_cam>;
928 #iommu-cells = <0>;
932 compatible = "samsung,exynos-sysmmu";
934 interrupt-parent = <&combiner>;
936 clock-names = "sysmmu", "master";
937 clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
938 power-domains = <&pd_cam>;
939 #iommu-cells = <0>;
943 compatible = "samsung,exynos-sysmmu";
945 interrupt-parent = <&combiner>;
947 clock-names = "sysmmu", "master";
948 clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
949 power-domains = <&pd_cam>;
950 #iommu-cells = <0>;
954 compatible = "samsung,exynos-sysmmu";
956 interrupt-parent = <&combiner>;
958 clock-names = "sysmmu", "master";
959 clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
960 power-domains = <&pd_cam>;
961 #iommu-cells = <0>;
965 compatible = "samsung,exynos-sysmmu";
967 interrupt-parent = <&combiner>;
969 clock-names = "sysmmu", "master";
970 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
971 power-domains = <&pd_cam>;
972 #iommu-cells = <0>;
976 compatible = "samsung,exynos-sysmmu";
978 interrupt-parent = <&combiner>;
980 clock-names = "sysmmu", "master";
981 clocks = <&clock CLK_SMMU_ROTATOR>,
982 <&clock CLK_ROTATOR>;
983 #iommu-cells = <0>;
987 compatible = "samsung,exynos-sysmmu";
989 interrupt-parent = <&combiner>;
991 clock-names = "sysmmu", "master";
992 clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
993 power-domains = <&pd_lcd0>;
994 #iommu-cells = <0>;
998 compatible = "samsung,exynos4210-secss";
1001 clocks = <&clock CLK_SSS>;
1002 clock-names = "secss";
1006 compatible = "samsung,exynos4-rng";
1008 clocks = <&clock CLK_SSS>;
1009 clock-names = "secss";
1014 #include "exynos-syscon-restart.dtsi"