Lines Matching +full:reg +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
15 #clock-cells = <0>;
16 compatible = "ti,dra7-atl-clock";
21 #clock-cells = <0>;
22 compatible = "ti,dra7-atl-clock";
27 #clock-cells = <0>;
28 compatible = "ti,dra7-atl-clock";
33 #clock-cells = <0>;
34 compatible = "fixed-clock";
35 clock-frequency = <0>;
39 #clock-cells = <0>;
40 compatible = "fixed-clock";
41 clock-frequency = <0>;
45 #clock-cells = <0>;
46 compatible = "fixed-clock";
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 compatible = "fixed-clock";
53 clock-frequency = <100000000>;
57 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 clock-frequency = <0>;
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <0>;
69 #clock-cells = <0>;
70 compatible = "fixed-clock";
71 clock-frequency = <0>;
75 #clock-cells = <0>;
76 compatible = "fixed-clock";
77 clock-frequency = <0>;
81 #clock-cells = <0>;
82 compatible = "fixed-clock";
83 clock-frequency = <0>;
87 #clock-cells = <0>;
88 compatible = "fixed-clock";
89 clock-frequency = <0>;
93 #clock-cells = <0>;
94 compatible = "fixed-clock";
95 clock-frequency = <32768>;
99 #clock-cells = <0>;
100 compatible = "fixed-clock";
101 clock-frequency = <32768>;
105 #clock-cells = <0>;
106 compatible = "fixed-factor-clock";
108 clock-mult = <1>;
109 clock-div = <610>;
113 #clock-cells = <0>;
114 compatible = "fixed-clock";
115 clock-frequency = <12000000>;
119 #clock-cells = <0>;
120 compatible = "fixed-clock";
121 clock-frequency = <13000000>;
125 #clock-cells = <0>;
126 compatible = "fixed-clock";
127 clock-frequency = <16800000>;
131 #clock-cells = <0>;
132 compatible = "fixed-clock";
133 clock-frequency = <19200000>;
137 #clock-cells = <0>;
138 compatible = "fixed-clock";
139 clock-frequency = <20000000>;
143 #clock-cells = <0>;
144 compatible = "fixed-clock";
145 clock-frequency = <26000000>;
149 #clock-cells = <0>;
150 compatible = "fixed-clock";
151 clock-frequency = <27000000>;
155 #clock-cells = <0>;
156 compatible = "fixed-clock";
157 clock-frequency = <38400000>;
161 #clock-cells = <0>;
162 compatible = "fixed-clock";
163 clock-frequency = <22579200>;
167 #clock-cells = <0>;
168 compatible = "fixed-clock";
169 clock-frequency = <0>;
173 #clock-cells = <0>;
174 compatible = "fixed-clock";
175 clock-frequency = <0>;
179 #clock-cells = <0>;
180 compatible = "fixed-clock";
181 clock-frequency = <0>;
185 #clock-cells = <0>;
186 compatible = "fixed-clock";
187 clock-frequency = <0>;
191 #clock-cells = <0>;
192 compatible = "fixed-clock";
193 clock-frequency = <0>;
197 #clock-cells = <0>;
198 compatible = "ti,omap4-dpll-m4xen-clock";
200 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
204 #clock-cells = <0>;
205 compatible = "ti,omap4-dpll-x2-clock";
210 #clock-cells = <0>;
211 compatible = "ti,divider-clock";
213 ti,max-div = <31>;
214 ti,autoidle-shift = <8>;
215 reg = <0x01f0>;
216 ti,index-starts-at-one;
217 ti,invert-autoidle-bit;
221 #clock-cells = <0>;
222 compatible = "ti,divider-clock";
224 ti,max-div = <4>;
225 reg = <0x0108>;
226 ti,index-power-of-two;
230 #clock-cells = <0>;
231 compatible = "ti,divider-clock";
233 ti,max-div = <31>;
234 ti,autoidle-shift = <8>;
235 reg = <0x01f0>;
236 ti,index-starts-at-one;
237 ti,invert-autoidle-bit;
241 #clock-cells = <0>;
242 compatible = "ti,divider-clock";
244 ti,max-div = <31>;
245 ti,autoidle-shift = <8>;
246 reg = <0x01f4>;
247 ti,index-starts-at-one;
248 ti,invert-autoidle-bit;
252 #clock-cells = <0>;
253 compatible = "ti,mux-clock";
255 ti,bit-shift = <23>;
256 reg = <0x012c>;
260 #clock-cells = <0>;
261 compatible = "ti,omap4-dpll-core-clock";
263 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
267 #clock-cells = <0>;
268 compatible = "ti,omap4-dpll-x2-clock";
273 #clock-cells = <0>;
274 compatible = "ti,divider-clock";
276 ti,max-div = <63>;
277 ti,autoidle-shift = <8>;
278 reg = <0x013c>;
279 ti,index-starts-at-one;
280 ti,invert-autoidle-bit;
284 #clock-cells = <0>;
285 compatible = "fixed-factor-clock";
287 clock-mult = <1>;
288 clock-div = <1>;
292 #clock-cells = <0>;
293 compatible = "ti,omap5-mpu-dpll-clock";
295 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
299 #clock-cells = <0>;
300 compatible = "ti,divider-clock";
302 ti,max-div = <31>;
303 ti,autoidle-shift = <8>;
304 reg = <0x0170>;
305 ti,index-starts-at-one;
306 ti,invert-autoidle-bit;
310 #clock-cells = <0>;
311 compatible = "fixed-factor-clock";
313 clock-mult = <1>;
314 clock-div = <1>;
318 #clock-cells = <0>;
319 compatible = "fixed-factor-clock";
321 clock-mult = <1>;
322 clock-div = <1>;
326 #clock-cells = <0>;
327 compatible = "ti,mux-clock";
329 ti,bit-shift = <23>;
330 reg = <0x0240>;
334 #clock-cells = <0>;
335 compatible = "ti,omap4-dpll-clock";
337 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
338 assigned-clocks = <&dpll_dsp_ck>;
339 assigned-clock-rates = <600000000>;
343 #clock-cells = <0>;
344 compatible = "ti,divider-clock";
346 ti,max-div = <31>;
347 ti,autoidle-shift = <8>;
348 reg = <0x0244>;
349 ti,index-starts-at-one;
350 ti,invert-autoidle-bit;
351 assigned-clocks = <&dpll_dsp_m2_ck>;
352 assigned-clock-rates = <600000000>;
356 #clock-cells = <0>;
357 compatible = "fixed-factor-clock";
359 clock-mult = <1>;
360 clock-div = <1>;
364 #clock-cells = <0>;
365 compatible = "ti,mux-clock";
367 ti,bit-shift = <23>;
368 reg = <0x01ac>;
372 #clock-cells = <0>;
373 compatible = "ti,omap4-dpll-clock";
375 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
376 assigned-clocks = <&dpll_iva_ck>;
377 assigned-clock-rates = <1165000000>;
381 #clock-cells = <0>;
382 compatible = "ti,divider-clock";
384 ti,max-div = <31>;
385 ti,autoidle-shift = <8>;
386 reg = <0x01b0>;
387 ti,index-starts-at-one;
388 ti,invert-autoidle-bit;
389 assigned-clocks = <&dpll_iva_m2_ck>;
390 assigned-clock-rates = <388333334>;
394 #clock-cells = <0>;
395 compatible = "fixed-factor-clock";
397 clock-mult = <1>;
398 clock-div = <1>;
402 #clock-cells = <0>;
403 compatible = "ti,mux-clock";
405 ti,bit-shift = <23>;
406 reg = <0x02e4>;
410 #clock-cells = <0>;
411 compatible = "ti,omap4-dpll-clock";
413 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
414 assigned-clocks = <&dpll_gpu_ck>;
415 assigned-clock-rates = <1277000000>;
419 #clock-cells = <0>;
420 compatible = "ti,divider-clock";
422 ti,max-div = <31>;
423 ti,autoidle-shift = <8>;
424 reg = <0x02e8>;
425 ti,index-starts-at-one;
426 ti,invert-autoidle-bit;
427 assigned-clocks = <&dpll_gpu_m2_ck>;
428 assigned-clock-rates = <425666667>;
432 #clock-cells = <0>;
433 compatible = "ti,divider-clock";
435 ti,max-div = <31>;
436 ti,autoidle-shift = <8>;
437 reg = <0x0130>;
438 ti,index-starts-at-one;
439 ti,invert-autoidle-bit;
443 #clock-cells = <0>;
444 compatible = "fixed-factor-clock";
446 clock-mult = <1>;
447 clock-div = <1>;
451 #clock-cells = <0>;
452 compatible = "ti,mux-clock";
454 ti,bit-shift = <23>;
455 reg = <0x021c>;
459 #clock-cells = <0>;
460 compatible = "ti,omap4-dpll-clock";
462 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
466 #clock-cells = <0>;
467 compatible = "ti,divider-clock";
469 ti,max-div = <31>;
470 ti,autoidle-shift = <8>;
471 reg = <0x0220>;
472 ti,index-starts-at-one;
473 ti,invert-autoidle-bit;
477 #clock-cells = <0>;
478 compatible = "ti,mux-clock";
480 ti,bit-shift = <23>;
481 reg = <0x02b4>;
485 #clock-cells = <0>;
486 compatible = "ti,omap4-dpll-clock";
488 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
492 #clock-cells = <0>;
493 compatible = "ti,divider-clock";
495 ti,max-div = <31>;
496 ti,autoidle-shift = <8>;
497 reg = <0x02b8>;
498 ti,index-starts-at-one;
499 ti,invert-autoidle-bit;
503 #clock-cells = <0>;
504 compatible = "fixed-factor-clock";
506 clock-mult = <1>;
507 clock-div = <1>;
511 #clock-cells = <0>;
512 compatible = "fixed-factor-clock";
514 clock-mult = <1>;
515 clock-div = <1>;
519 #clock-cells = <0>;
520 compatible = "fixed-factor-clock";
522 clock-mult = <1>;
523 clock-div = <1>;
527 #clock-cells = <0>;
528 compatible = "fixed-factor-clock";
530 clock-mult = <1>;
531 clock-div = <2>;
535 #clock-cells = <0>;
536 compatible = "fixed-factor-clock";
538 clock-mult = <1>;
539 clock-div = <3>;
543 #clock-cells = <0>;
544 compatible = "fixed-factor-clock";
546 clock-mult = <1>;
547 clock-div = <1>;
551 #clock-cells = <0>;
552 compatible = "ti,mux-clock";
554 ti,bit-shift = <23>;
555 reg = <0x0290>;
559 #clock-cells = <0>;
560 compatible = "ti,omap4-dpll-clock";
562 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
566 #clock-cells = <0>;
567 compatible = "ti,divider-clock";
569 ti,max-div = <31>;
570 ti,autoidle-shift = <8>;
571 reg = <0x0294>;
572 ti,index-starts-at-one;
573 ti,invert-autoidle-bit;
577 #clock-cells = <0>;
578 compatible = "fixed-factor-clock";
580 clock-mult = <1>;
581 clock-div = <1>;
585 #clock-cells = <0>;
586 compatible = "ti,divider-clock";
588 ti,max-div = <63>;
589 ti,autoidle-shift = <8>;
590 reg = <0x0140>;
591 ti,index-starts-at-one;
592 ti,invert-autoidle-bit;
596 #clock-cells = <0>;
597 compatible = "ti,divider-clock";
599 ti,max-div = <63>;
600 ti,autoidle-shift = <8>;
601 reg = <0x0144>;
602 ti,index-starts-at-one;
603 ti,invert-autoidle-bit;
607 #clock-cells = <0>;
608 compatible = "ti,divider-clock";
610 ti,max-div = <63>;
611 ti,autoidle-shift = <8>;
612 reg = <0x0154>;
613 ti,index-starts-at-one;
614 ti,invert-autoidle-bit;
618 #clock-cells = <0>;
619 compatible = "ti,divider-clock";
621 ti,max-div = <63>;
622 ti,autoidle-shift = <8>;
623 reg = <0x0158>;
624 ti,index-starts-at-one;
625 ti,invert-autoidle-bit;
629 #clock-cells = <0>;
630 compatible = "ti,divider-clock";
632 ti,max-div = <63>;
633 ti,autoidle-shift = <8>;
634 reg = <0x015c>;
635 ti,index-starts-at-one;
636 ti,invert-autoidle-bit;
640 #clock-cells = <0>;
641 compatible = "ti,omap4-dpll-x2-clock";
646 #clock-cells = <0>;
647 compatible = "ti,divider-clock";
649 ti,max-div = <63>;
650 ti,autoidle-shift = <8>;
651 reg = <0x0228>;
652 ti,index-starts-at-one;
653 ti,invert-autoidle-bit;
657 #clock-cells = <0>;
658 compatible = "ti,omap4-dpll-x2-clock";
663 #clock-cells = <0>;
664 compatible = "ti,divider-clock";
666 ti,max-div = <31>;
667 ti,autoidle-shift = <8>;
668 reg = <0x0248>;
669 ti,index-starts-at-one;
670 ti,invert-autoidle-bit;
671 assigned-clocks = <&dpll_dsp_m3x2_ck>;
672 assigned-clock-rates = <400000000>;
676 #clock-cells = <0>;
677 compatible = "ti,omap4-dpll-x2-clock";
682 #clock-cells = <0>;
683 compatible = "ti,divider-clock";
685 ti,max-div = <63>;
686 ti,autoidle-shift = <8>;
687 reg = <0x02c0>;
688 ti,index-starts-at-one;
689 ti,invert-autoidle-bit;
693 #clock-cells = <0>;
694 compatible = "ti,divider-clock";
696 ti,max-div = <63>;
697 ti,autoidle-shift = <8>;
698 reg = <0x02c4>;
699 ti,index-starts-at-one;
700 ti,invert-autoidle-bit;
704 #clock-cells = <0>;
705 compatible = "ti,divider-clock";
707 ti,max-div = <63>;
708 ti,autoidle-shift = <8>;
709 reg = <0x02c8>;
710 ti,index-starts-at-one;
711 ti,invert-autoidle-bit;
715 #clock-cells = <0>;
716 compatible = "ti,divider-clock";
718 ti,max-div = <31>;
719 ti,autoidle-shift = <8>;
720 reg = <0x02bc>;
721 ti,index-starts-at-one;
722 ti,invert-autoidle-bit;
726 #clock-cells = <0>;
727 compatible = "fixed-factor-clock";
729 clock-mult = <1>;
730 clock-div = <2>;
734 #clock-cells = <0>;
735 compatible = "fixed-factor-clock";
737 clock-mult = <1>;
738 clock-div = <1>;
742 #clock-cells = <0>;
743 compatible = "fixed-factor-clock";
745 clock-mult = <1>;
746 clock-div = <1>;
750 #clock-cells = <0>;
751 compatible = "ti,divider-clock";
752 ti,max-div = <2>;
753 ti,bit-shift = <4>;
754 reg = <0x0100>;
756 ti,index-power-of-two;
760 #clock-cells = <0>;
761 compatible = "fixed-factor-clock";
763 clock-mult = <1>;
764 clock-div = <2>;
768 #clock-cells = <0>;
769 compatible = "fixed-factor-clock";
771 clock-mult = <1>;
772 clock-div = <1>;
776 #clock-cells = <0>;
777 compatible = "fixed-factor-clock";
779 clock-mult = <1>;
780 clock-div = <1>;
784 #clock-cells = <0>;
785 compatible = "fixed-factor-clock";
787 clock-mult = <1>;
788 clock-div = <1>;
792 #clock-cells = <0>;
793 compatible = "fixed-factor-clock";
795 clock-mult = <1>;
796 clock-div = <1>;
800 #clock-cells = <0>;
801 compatible = "fixed-clock";
802 clock-frequency = <0>;
807 #clock-cells = <0>;
808 compatible = "ti,mux-clock";
810 reg = <0x0110>;
811 ti,index-starts-at-one;
815 #clock-cells = <0>;
816 compatible = "ti,mux-clock";
818 reg = <0x0118>;
822 #clock-cells = <0>;
823 compatible = "ti,mux-clock";
825 reg = <0x0114>;
829 #clock-cells = <0>;
830 compatible = "ti,mux-clock";
832 reg = <0x010c>;
836 #clock-cells = <0>;
837 compatible = "ti,divider-clock";
839 reg = <0x011c>;
844 #clock-cells = <0>;
845 compatible = "ti,divider-clock";
847 reg = <0x0178>;
848 ti,max-div = <2>;
852 #clock-cells = <0>;
853 compatible = "ti,divider-clock";
855 reg = <0x0174>;
856 ti,max-div = <2>;
860 #clock-cells = <0>;
861 compatible = "ti,divider-clock";
863 reg = <0x01d8>;
868 #clock-cells = <0>;
869 compatible = "ti,divider-clock";
871 reg = <0x0120>;
872 ti,max-div = <2>;
876 #clock-cells = <0>;
877 compatible = "ti,mux-clock";
879 reg = <0x01dc>;
883 #clock-cells = <0>;
884 compatible = "ti,divider-clock";
886 ti,max-div = <64>;
887 reg = <0x01c8>;
888 ti,index-power-of-two;
892 #clock-cells = <0>;
893 compatible = "ti,divider-clock";
895 ti,max-div = <64>;
896 reg = <0x01cc>;
897 ti,index-power-of-two;
901 #clock-cells = <0>;
902 compatible = "ti,divider-clock";
904 ti,max-div = <64>;
905 reg = <0x01bc>;
906 ti,index-power-of-two;
910 #clock-cells = <0>;
911 compatible = "ti,divider-clock";
913 ti,max-div = <64>;
914 reg = <0x018c>;
915 ti,index-power-of-two;
919 #clock-cells = <0>;
920 compatible = "ti,divider-clock";
922 ti,max-div = <64>;
923 reg = <0x01a0>;
924 ti,index-power-of-two;
928 #clock-cells = <0>;
929 compatible = "ti,divider-clock";
931 ti,max-div = <64>;
932 reg = <0x0190>;
933 ti,index-power-of-two;
937 #clock-cells = <0>;
938 compatible = "ti,divider-clock";
940 ti,max-div = <64>;
941 reg = <0x019c>;
942 ti,index-power-of-two;
946 #clock-cells = <0>;
947 compatible = "fixed-factor-clock";
949 clock-mult = <1>;
950 clock-div = <2>;
954 #clock-cells = <0>;
955 compatible = "ti,divider-clock";
957 ti,max-div = <64>;
958 reg = <0x01ac>;
959 ti,index-power-of-two;
963 #clock-cells = <0>;
964 compatible = "ti,divider-clock";
966 ti,max-div = <64>;
967 reg = <0x0184>;
968 ti,index-power-of-two;
972 #clock-cells = <0>;
973 compatible = "ti,divider-clock";
975 ti,max-div = <64>;
976 reg = <0x01c0>;
977 ti,index-power-of-two;
981 #clock-cells = <0>;
982 compatible = "ti,divider-clock";
984 ti,max-div = <64>;
985 reg = <0x01b8>;
986 ti,index-power-of-two;
990 #clock-cells = <0>;
991 compatible = "ti,divider-clock";
993 ti,max-div = <64>;
994 reg = <0x01b4>;
995 ti,index-power-of-two;
999 #clock-cells = <0>;
1000 compatible = "ti,divider-clock";
1002 ti,max-div = <64>;
1003 reg = <0x0194>;
1004 ti,index-power-of-two;
1008 #clock-cells = <0>;
1009 compatible = "ti,divider-clock";
1011 ti,max-div = <64>;
1012 reg = <0x01c4>;
1013 ti,index-power-of-two;
1017 #clock-cells = <0>;
1018 compatible = "ti,mux-clock";
1020 reg = <0x0158>;
1024 #clock-cells = <0>;
1025 compatible = "ti,mux-clock";
1027 reg = <0x015c>;
1031 #clock-cells = <0>;
1032 compatible = "ti,mux-clock";
1034 reg = <0x0160>;
1038 #clock-cells = <0>;
1039 compatible = "fixed-factor-clock";
1041 clock-mult = <1>;
1042 clock-div = <2>;
1046 #clock-cells = <0>;
1047 compatible = "ti,mux-clock";
1049 reg = <0x0180>;
1053 #clock-cells = <0>;
1054 compatible = "ti,mux-clock";
1056 reg = <0x0164>;
1060 #clock-cells = <0>;
1061 compatible = "ti,divider-clock";
1063 ti,max-div = <64>;
1064 reg = <0x0134>;
1065 ti,index-power-of-two;
1069 #clock-cells = <0>;
1070 compatible = "ti,divider-clock";
1072 ti,max-div = <64>;
1073 reg = <0x0130>;
1074 ti,index-power-of-two;
1078 #clock-cells = <0>;
1079 compatible = "ti,divider-clock";
1081 ti,max-div = <64>;
1082 reg = <0x0138>;
1083 ti,index-power-of-two;
1087 #clock-cells = <0>;
1088 compatible = "ti,divider-clock";
1090 reg = <0x0144>;
1091 ti,max-div = <2>;
1095 #clock-cells = <0>;
1096 compatible = "ti,mux-clock";
1098 reg = <0x0168>;
1102 #clock-cells = <0>;
1103 compatible = "ti,mux-clock";
1105 reg = <0x016c>;
1109 #clock-cells = <0>;
1110 compatible = "ti,mux-clock";
1112 reg = <0x0108>;
1118 #clock-cells = <0>;
1119 compatible = "ti,omap4-dpll-clock";
1121 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
1125 #clock-cells = <0>;
1126 compatible = "ti,divider-clock";
1128 ti,max-div = <31>;
1129 ti,autoidle-shift = <8>;
1130 reg = <0x0210>;
1131 ti,index-starts-at-one;
1132 ti,invert-autoidle-bit;
1136 compatible = "ti,mux-clock";
1138 #clock-cells = <0>;
1139 reg = <0x021c 0x4>;
1140 ti,bit-shift = <7>;
1144 #clock-cells = <0>;
1145 compatible = "ti,dra7-apll-clock";
1147 reg = <0x021c>, <0x0220>;
1151 compatible = "ti,divider-clock";
1153 #clock-cells = <0>;
1154 reg = <0x021c>;
1156 ti,bit-shift = <8>;
1157 ti,max-div = <2>;
1161 #clock-cells = <0>;
1162 compatible = "fixed-factor-clock";
1164 clock-mult = <1>;
1165 clock-div = <1>;
1169 #clock-cells = <0>;
1170 compatible = "fixed-factor-clock";
1172 clock-mult = <1>;
1173 clock-div = <1>;
1177 #clock-cells = <0>;
1178 compatible = "fixed-factor-clock";
1180 clock-mult = <1>;
1181 clock-div = <1>;
1185 #clock-cells = <0>;
1186 compatible = "ti,mux-clock";
1188 ti,bit-shift = <23>;
1189 reg = <0x014c>;
1193 #clock-cells = <0>;
1194 compatible = "ti,omap4-dpll-clock";
1196 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1200 #clock-cells = <0>;
1201 compatible = "ti,divider-clock";
1203 ti,max-div = <31>;
1204 ti,autoidle-shift = <8>;
1205 reg = <0x0150>;
1206 ti,index-starts-at-one;
1207 ti,invert-autoidle-bit;
1211 #clock-cells = <0>;
1212 compatible = "fixed-factor-clock";
1214 clock-mult = <1>;
1215 clock-div = <1>;
1219 #clock-cells = <0>;
1220 compatible = "ti,mux-clock";
1222 ti,bit-shift = <23>;
1223 reg = <0x018c>;
1227 #clock-cells = <0>;
1228 compatible = "ti,omap4-dpll-j-type-clock";
1230 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1234 #clock-cells = <0>;
1235 compatible = "ti,divider-clock";
1237 ti,max-div = <127>;
1238 ti,autoidle-shift = <8>;
1239 reg = <0x0190>;
1240 ti,index-starts-at-one;
1241 ti,invert-autoidle-bit;
1245 #clock-cells = <0>;
1246 compatible = "ti,divider-clock";
1248 ti,max-div = <127>;
1249 ti,autoidle-shift = <8>;
1250 reg = <0x0210>;
1251 ti,index-starts-at-one;
1252 ti,invert-autoidle-bit;
1256 #clock-cells = <0>;
1257 compatible = "ti,omap4-dpll-x2-clock";
1262 #clock-cells = <0>;
1263 compatible = "ti,divider-clock";
1265 ti,max-div = <63>;
1266 ti,autoidle-shift = <8>;
1267 reg = <0x0158>;
1268 ti,index-starts-at-one;
1269 ti,invert-autoidle-bit;
1273 #clock-cells = <0>;
1274 compatible = "ti,divider-clock";
1276 ti,max-div = <63>;
1277 ti,autoidle-shift = <8>;
1278 reg = <0x015c>;
1279 ti,index-starts-at-one;
1280 ti,invert-autoidle-bit;
1284 #clock-cells = <0>;
1285 compatible = "ti,divider-clock";
1287 ti,max-div = <63>;
1288 ti,autoidle-shift = <8>;
1289 reg = <0x0160>;
1290 ti,index-starts-at-one;
1291 ti,invert-autoidle-bit;
1295 #clock-cells = <0>;
1296 compatible = "ti,divider-clock";
1298 ti,max-div = <63>;
1299 ti,autoidle-shift = <8>;
1300 reg = <0x0164>;
1301 ti,index-starts-at-one;
1302 ti,invert-autoidle-bit;
1306 #clock-cells = <0>;
1307 compatible = "ti,divider-clock";
1309 ti,max-div = <31>;
1310 ti,autoidle-shift = <8>;
1311 reg = <0x0150>;
1312 ti,index-starts-at-one;
1313 ti,invert-autoidle-bit;
1317 #clock-cells = <0>;
1318 compatible = "fixed-factor-clock";
1320 clock-mult = <1>;
1321 clock-div = <1>;
1325 #clock-cells = <0>;
1326 compatible = "fixed-factor-clock";
1328 clock-mult = <1>;
1329 clock-div = <2>;
1333 #clock-cells = <0>;
1334 compatible = "fixed-factor-clock";
1336 clock-mult = <1>;
1337 clock-div = <16>;
1341 #clock-cells = <0>;
1342 compatible = "fixed-factor-clock";
1344 clock-mult = <1>;
1345 clock-div = <4>;
1349 #clock-cells = <0>;
1350 compatible = "fixed-factor-clock";
1352 clock-mult = <1>;
1353 clock-div = <4>;
1357 #clock-cells = <0>;
1358 compatible = "fixed-factor-clock";
1360 clock-mult = <1>;
1361 clock-div = <2>;
1365 #clock-cells = <0>;
1366 compatible = "ti,divider-clock";
1368 reg = <0x0104>;
1373 #clock-cells = <0>;
1374 compatible = "ti,gate-clock";
1376 ti,bit-shift = <8>;
1377 reg = <0x06b0>;
1381 #clock-cells = <0>;
1382 compatible = "ti,gate-clock";
1384 ti,bit-shift = <8>;
1385 reg = <0x06c0>;
1389 #clock-cells = <0>;
1390 compatible = "ti,gate-clock";
1392 ti,bit-shift = <8>;
1393 reg = <0x0640>;
1397 #clock-cells = <0>;
1398 compatible = "ti,gate-clock";
1400 ti,bit-shift = <8>;
1401 reg = <0x0688>;
1405 #clock-cells = <0>;
1406 compatible = "ti,gate-clock";
1408 ti,bit-shift = <8>;
1409 reg = <0x0698>;
1413 #clock-cells = <0>;
1414 compatible = "ti,mux-clock";
1416 ti,bit-shift = <24>;
1417 reg = <0x1220>;
1418 assigned-clocks = <&gpu_core_gclk_mux>;
1419 assigned-clock-parents = <&dpll_gpu_m2_ck>;
1423 #clock-cells = <0>;
1424 compatible = "ti,mux-clock";
1426 ti,bit-shift = <26>;
1427 reg = <0x1220>;
1428 assigned-clocks = <&gpu_hyd_gclk_mux>;
1429 assigned-clock-parents = <&dpll_gpu_m2_ck>;
1433 #clock-cells = <0>;
1434 compatible = "ti,divider-clock";
1436 ti,bit-shift = <24>;
1437 reg = <0x0e50>;
1442 #clock-cells = <0>;
1443 compatible = "ti,mux-clock";
1445 ti,bit-shift = <24>;
1446 reg = <0x1020>;
1450 #clock-cells = <0>;
1451 compatible = "ti,mux-clock";
1453 ti,bit-shift = <24>;
1454 reg = <0x1028>;
1458 #clock-cells = <0>;
1459 compatible = "ti,mux-clock";
1461 ti,bit-shift = <24>;
1462 reg = <0x1030>;
1475 #clock-cells = <0>;
1476 compatible = "ti,gate-clock";
1478 ti,bit-shift = <0>;
1479 reg = <0x558>;
1483 #clock-cells = <0>;
1484 compatible = "ti,gate-clock";
1486 ti,bit-shift = <20>;
1487 reg = <0x0558>;
1491 #clock-cells = <0>;
1492 compatible = "ti,gate-clock";
1494 ti,bit-shift = <21>;
1495 reg = <0x0558>;
1499 #clock-cells = <0>;
1500 compatible = "ti,gate-clock";
1502 ti,bit-shift = <22>;
1503 reg = <0x0558>;
1507 #clock-cells = <0>;
1508 compatible = "ti,mux-clock";
1510 ti,bit-shift = <8>;
1511 reg = <0x6c4>;
1516 mpu_cm: mpu-cm@300 {
1517 compatible = "ti,omap4-cm";
1518 reg = <0x300 0x100>;
1519 #address-cells = <1>;
1520 #size-cells = <1>;
1523 mpu_clkctrl: mpu-clkctrl@20 {
1525 reg = <0x20 0x4>;
1526 #clock-cells = <2>;
1531 dsp1_cm: dsp1-cm@400 {
1532 compatible = "ti,omap4-cm";
1533 reg = <0x400 0x100>;
1534 #address-cells = <1>;
1535 #size-cells = <1>;
1538 dsp1_clkctrl: dsp1-clkctrl@20 {
1540 reg = <0x20 0x4>;
1541 #clock-cells = <2>;
1546 ipu_cm: ipu-cm@500 {
1547 compatible = "ti,omap4-cm";
1548 reg = <0x500 0x100>;
1549 #address-cells = <1>;
1550 #size-cells = <1>;
1553 ipu1_clkctrl: ipu1-clkctrl@20 {
1555 reg = <0x20 0x4>;
1556 #clock-cells = <2>;
1557 assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>;
1558 assigned-clock-parents = <&dpll_core_h22x2_ck>;
1561 ipu_clkctrl: ipu-clkctrl@50 {
1563 reg = <0x50 0x34>;
1564 #clock-cells = <2>;
1569 dsp2_cm: dsp2-cm@600 {
1570 compatible = "ti,omap4-cm";
1571 reg = <0x600 0x100>;
1572 #address-cells = <1>;
1573 #size-cells = <1>;
1576 dsp2_clkctrl: dsp2-clkctrl@20 {
1578 reg = <0x20 0x4>;
1579 #clock-cells = <2>;
1584 rtc_cm: rtc-cm@700 {
1585 compatible = "ti,omap4-cm";
1586 reg = <0x700 0x60>;
1587 #address-cells = <1>;
1588 #size-cells = <1>;
1591 rtc_clkctrl: rtc-clkctrl@20 {
1593 reg = <0x20 0x28>;
1594 #clock-cells = <2>;
1598 vpe_cm: vpe-cm@760 {
1599 compatible = "ti,omap4-cm";
1600 reg = <0x760 0xc>;
1601 #address-cells = <1>;
1602 #size-cells = <1>;
1605 vpe_clkctrl: vpe-clkctrl@0 {
1607 reg = <0x0 0xc>;
1608 #clock-cells = <2>;
1615 coreaon_cm: coreaon-cm@600 {
1616 compatible = "ti,omap4-cm";
1617 reg = <0x600 0x100>;
1618 #address-cells = <1>;
1619 #size-cells = <1>;
1622 coreaon_clkctrl: coreaon-clkctrl@20 {
1624 reg = <0x20 0x1c>;
1625 #clock-cells = <2>;
1629 l3main1_cm: l3main1-cm@700 {
1630 compatible = "ti,omap4-cm";
1631 reg = <0x700 0x100>;
1632 #address-cells = <1>;
1633 #size-cells = <1>;
1636 l3main1_clkctrl: l3main1-clkctrl@20 {
1638 reg = <0x20 0x74>;
1639 #clock-cells = <2>;
1644 ipu2_cm: ipu2-cm@900 {
1645 compatible = "ti,omap4-cm";
1646 reg = <0x900 0x100>;
1647 #address-cells = <1>;
1648 #size-cells = <1>;
1651 ipu2_clkctrl: ipu2-clkctrl@20 {
1653 reg = <0x20 0x4>;
1654 #clock-cells = <2>;
1659 dma_cm: dma-cm@a00 {
1660 compatible = "ti,omap4-cm";
1661 reg = <0xa00 0x100>;
1662 #address-cells = <1>;
1663 #size-cells = <1>;
1666 dma_clkctrl: dma-clkctrl@20 {
1668 reg = <0x20 0x4>;
1669 #clock-cells = <2>;
1673 emif_cm: emif-cm@b00 {
1674 compatible = "ti,omap4-cm";
1675 reg = <0xb00 0x100>;
1676 #address-cells = <1>;
1677 #size-cells = <1>;
1680 emif_clkctrl: emif-clkctrl@20 {
1682 reg = <0x20 0x4>;
1683 #clock-cells = <2>;
1687 atl_cm: atl-cm@c00 {
1688 compatible = "ti,omap4-cm";
1689 reg = <0xc00 0x100>;
1690 #address-cells = <1>;
1691 #size-cells = <1>;
1694 atl_clkctrl: atl-clkctrl@0 {
1696 reg = <0x0 0x4>;
1697 #clock-cells = <2>;
1701 l4cfg_cm: l4cfg-cm@d00 {
1702 compatible = "ti,omap4-cm";
1703 reg = <0xd00 0x100>;
1704 #address-cells = <1>;
1705 #size-cells = <1>;
1708 l4cfg_clkctrl: l4cfg-clkctrl@20 {
1710 reg = <0x20 0x84>;
1711 #clock-cells = <2>;
1715 l3instr_cm: l3instr-cm@e00 {
1716 compatible = "ti,omap4-cm";
1717 reg = <0xe00 0x100>;
1718 #address-cells = <1>;
1719 #size-cells = <1>;
1722 l3instr_clkctrl: l3instr-clkctrl@20 {
1724 reg = <0x20 0xc>;
1725 #clock-cells = <2>;
1729 cam_cm: cam-cm@1000 {
1730 compatible = "ti,omap4-cm";
1731 reg = <0x1000 0x100>;
1732 #address-cells = <1>;
1733 #size-cells = <1>;
1736 cam_clkctrl: cam-clkctrl@20 {
1738 reg = <0x20 0x2c>;
1739 #clock-cells = <2>;
1743 dss_cm: dss-cm@1100 {
1744 compatible = "ti,omap4-cm";
1745 reg = <0x1100 0x100>;
1746 #address-cells = <1>;
1747 #size-cells = <1>;
1750 dss_clkctrl: dss-clkctrl@20 {
1752 reg = <0x20 0x14>;
1753 #clock-cells = <2>;
1757 gpu_cm: gpu-cm@1200 {
1758 compatible = "ti,omap4-cm";
1759 reg = <0x1200 0x100>;
1760 #address-cells = <1>;
1761 #size-cells = <1>;
1764 gpu_clkctrl: gpu-clkctrl@20 {
1766 reg = <0x20 0x4>;
1767 #clock-cells = <2>;
1771 l3init_cm: l3init-cm@1300 {
1772 compatible = "ti,omap4-cm";
1773 reg = <0x1300 0x100>;
1774 #address-cells = <1>;
1775 #size-cells = <1>;
1778 l3init_clkctrl: l3init-clkctrl@20 {
1780 reg = <0x20 0x6c>, <0xe0 0x14>;
1781 #clock-cells = <2>;
1784 pcie_clkctrl: pcie-clkctrl@b0 {
1786 reg = <0xb0 0xc>;
1787 #clock-cells = <2>;
1790 gmac_clkctrl: gmac-clkctrl@d0 {
1792 reg = <0xd0 0x4>;
1793 #clock-cells = <2>;
1798 l4per_cm: l4per-cm@1700 {
1799 compatible = "ti,omap4-cm";
1800 reg = <0x1700 0x300>;
1801 #address-cells = <1>;
1802 #size-cells = <1>;
1805 l4per_clkctrl: l4per-clkctrl@28 {
1807 reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>;
1808 #clock-cells = <2>;
1810 assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
1811 assigned-clock-parents = <&abe_24m_fclk>;
1814 l4sec_clkctrl: l4sec-clkctrl@1a0 {
1816 reg = <0x1a0 0x2c>;
1817 #clock-cells = <2>;
1820 l4per2_clkctrl: l4per2-clkctrl@c {
1822 …reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d…
1823 #clock-cells = <2>;
1826 l4per3_clkctrl: l4per3-clkctrl@14 {
1828 reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>;
1829 #clock-cells = <2>;
1836 wkupaon_cm: wkupaon-cm@1800 {
1837 compatible = "ti,omap4-cm";
1838 reg = <0x1800 0x100>;
1839 #address-cells = <1>;
1840 #size-cells = <1>;
1843 wkupaon_clkctrl: wkupaon-clkctrl@20 {
1845 reg = <0x20 0x6c>;
1846 #clock-cells = <2>;