Lines Matching +full:0 +full:x2000
31 #size-cells = <0>;
32 cpu@0 {
35 reg = <0>;
65 reg = <0x44000000 0x10000>;
73 reg = <0x48180000 0x4000>;
76 ranges = <0 0x48180000 0x4000>;
80 #size-cells = <0>;
89 reg = <0x48140000 0x21000>;
93 ranges = <0 0x48140000 0x21000>;
97 reg = <0x800 0x50a>;
99 #size-cells = <0>;
102 pinctrl-single,function-mask = <0xf>;
108 reg = <0x600 0x110>;
111 ranges = <0 0x600 0x110>;
115 reg = <0x20 0x8>;
119 #phy-cells = <0>;
125 reg = <0x28 0x8>;
129 #phy-cells = <0>;
136 #size-cells = <0>;
145 reg = <0x49000000 0x4>;
147 clocks = <&alwon_clkctrl DM816_TPCC_CLKCTRL 0>;
151 ranges = <0x0 0x49000000 0x10000>;
153 edma: dma@0 {
155 reg = <0 0x10000>;
164 <&edma_tptc2 3>, <&edma_tptc3 0>;
172 reg = <0x49800000 0x4>,
173 <0x49800010 0x4>;
179 clocks = <&alwon_clkctrl DM816_TPTC0_CLKCTRL 0>;
183 ranges = <0x0 0x49800000 0x100000>;
185 edma_tptc0: dma@0 {
187 reg = <0 0x100000>;
195 reg = <0x49900000 0x4>,
196 <0x49900010 0x4>;
202 clocks = <&alwon_clkctrl DM816_TPTC1_CLKCTRL 0>;
206 ranges = <0x0 0x49900000 0x100000>;
208 edma_tptc1: dma@0 {
210 reg = <0 0x100000>;
218 reg = <0x49a00000 0x4>,
219 <0x49a00010 0x4>;
225 clocks = <&alwon_clkctrl DM816_TPTC2_CLKCTRL 0>;
229 ranges = <0x0 0x49a00000 0x100000>;
231 edma_tptc2: dma@0 {
233 reg = <0 0x100000>;
241 reg = <0x49b00000 0x4>,
242 <0x49b00010 0x4>;
248 clocks = <&alwon_clkctrl DM816_TPTC3_CLKCTRL 0>;
252 ranges = <0x0 0x49b00000 0x100000>;
254 edma_tptc3: dma@0 {
256 reg = <0 0x100000>;
265 reg = <0x48080000 0x2000>;
273 reg = <0x48032000 0x1000>;
285 reg = <0x4804c000 0x1000>;
296 reg = <0x50000000 0x2000>;
300 dmas = <&edma 52 0>;
313 reg = <0x48028000 0x1000>;
315 #size-cells = <0>;
317 dmas = <&edma 58 0 &edma 59 0>;
324 reg = <0x4802a000 0x1000>;
326 #size-cells = <0>;
328 dmas = <&edma 60 0 &edma 61 0>;
336 reg = <0x48200000 0x1000>;
341 reg = <0x480c0000 0x1000>;
348 reg = <0x480c8000 0x2000>;
355 ti,mbox-tx = <3 0 0>;
356 ti,mbox-rx = <0 0 0>;
362 reg = <0x480ca000 0x2000>;
370 #size-cells = <0>;
371 reg = <0x4a100800 0x100>;
374 phy0: ethernet-phy@0 {
385 reg = <0x4a100000 0x800
386 0x4a100900 0x3700>;
389 ti,davinci-ctrl-reg-offset = <0>;
390 ti,davinci-ctrl-mod-reg-offset = <0x900>;
391 ti,davinci-ctrl-ram-offset = <0x2000>;
392 ti,davinci-ctrl-ram-size = <0x2000>;
400 reg = <0x4a120000 0x4000>;
403 ti,davinci-ctrl-reg-offset = <0>;
404 ti,davinci-ctrl-mod-reg-offset = <0x900>;
405 ti,davinci-ctrl-ram-offset = <0x2000>;
406 ti,davinci-ctrl-ram-size = <0x2000>;
413 reg = <0x4a140000 0x10000>;
420 reg = <0x48030000 0x1000>;
422 #size-cells = <0>;
426 dmas = <&edma 16 0 &edma 17 0
427 &edma 18 0 &edma 19 0
428 &edma 20 0 &edma 21 0
429 &edma 22 0 &edma 23 0>;
436 reg = <0x48060000 0x11000>;
439 dmas = <&edma 24 0 &edma 25 0>;
445 reg = <0x4802e000 0x4>,
446 <0x4802e010 0x4>;
453 clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
457 ranges = <0x0 0x4802e000 0x1000>;
459 timer1: timer@0 {
461 reg = <0 0x1000>;
464 clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
471 reg = <0x48040000 0x4>,
472 <0x48040010 0x4>;
479 clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
483 ranges = <0x0 0x48040000 0x1000>;
485 timer2: timer@0 {
487 reg = <0 0x1000>;
489 clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
496 reg = <0x48042000 0x2000>;
503 reg = <0x48044000 0x2000>;
511 reg = <0x48046000 0x2000>;
519 reg = <0x48048000 0x2000>;
527 reg = <0x4804a000 0x2000>;
536 reg = <0x48020000 0x2000>;
539 dmas = <&edma 26 0 &edma 27 0>;
546 reg = <0x48022000 0x2000>;
549 dmas = <&edma 28 0 &edma 29 0>;
556 reg = <0x48024000 0x2000>;
559 dmas = <&edma 30 0 &edma 31 0>;
566 reg = <0x47401000 0x400000>;
574 reg = <0x47401400 0x400
575 0x47401000 0x200>;
580 interface-type = <0>;
588 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
589 &cppi41dma 2 0 &cppi41dma 3 0
590 &cppi41dma 4 0 &cppi41dma 5 0
591 &cppi41dma 6 0 &cppi41dma 7 0
592 &cppi41dma 8 0 &cppi41dma 9 0
593 &cppi41dma 10 0 &cppi41dma 11 0
594 &cppi41dma 12 0 &cppi41dma 13 0
595 &cppi41dma 14 0 &cppi41dma 0 1
614 reg = <0x47401c00 0x400
615 0x47401800 0x200>;
620 interface-type = <0>;
628 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
629 &cppi41dma 17 0 &cppi41dma 18 0
630 &cppi41dma 19 0 &cppi41dma 20 0
631 &cppi41dma 21 0 &cppi41dma 22 0
632 &cppi41dma 23 0 &cppi41dma 24 0
633 &cppi41dma 25 0 &cppi41dma 26 0
634 &cppi41dma 27 0 &cppi41dma 28 0
635 &cppi41dma 29 0 &cppi41dma 15 1
654 reg = <0x47400000 0x1000
655 0x47402000 0x1000
656 0x47403000 0x1000
657 0x47404000 0x4000>;
670 reg = <0x480c2000 0x1000>;
671 interrupts = <0>;
682 timer@0 {
692 timer@0 {