boot/dts/bcm63138.dtsi

1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 	#address-cells = <1>;
11 	#size-cells = <1>;
14 	interrupt-parent = <&gic>;
22 		#address-cells = <1>;
23 		#size-cells = <0>;
27 			compatible = "arm,cortex-a9";
28 			next-level-cache = <&L2>;
29 			reg = <0>;
30 			enable-method = "brcm,bcm63138";
35 			compatible = "arm,cortex-a9";
36 			next-level-cache = <&L2>;
37 			reg = <1>;
38 			enable-method = "brcm,bcm63138";
46 			#clock-cells = <0>;
47 			compatible = "fixed-clock";
48 			clock-frequency = <50000000>;
49 			clock-output-names = "periph";
54 			#clock-cells = <0>;
55 			compatible = "fixed-factor-clock";
57 			clock-div = <2>;
58 			clock-mult = <1>;
63 			#clock-cells = <0>;
64 			compatible = "fixed-factor-clock";
66 			clock-div = <4>;
67 			clock-mult = <1>;
73 		compatible = "simple-bus";
75 		#address-cells = <1>;
76 		#size-cells = <1>;
78 		L2: cache-controller@1d000 {
79 			compatible = "arm,pl310-cache";
80 			reg = <0x1d000 0x1000>;
81 			cache-unified;
82 			cache-level = <2>;
83 			cache-size = <524288>;
84 			cache-sets = <1024>;
85 			cache-line-size = <32>;
90 			compatible = "arm,cortex-a9-scu";
91 			reg = <0x1e000 0x100>;
94 		gic: interrupt-controller@1f000 {
95 			compatible = "arm,cortex-a9-gic";
96 			reg = <0x1f000 0x1000
98 			#interrupt-cells = <3>;
99 			#address-cells = <0>;
100 			interrupt-controller;
104 			compatible = "arm,cortex-a9-global-timer";
105 			reg = <0x1e200 0x20>;
110 		local_timer: local-timer@1e600 {
111 			compatible = "arm,cortex-a9-twd-timer";
112 			reg = <0x1e600 0x20>;
119 			compatible = "arm,cortex-a9-twd-wdt";
120 			reg = <0x1e620 0x20>;
126 			#clock-cells = <0>;
127 			compatible = "brcm,bcm63138-armpll";
129 			reg = <0x20000 0xf00>;
132 		pmb0: reset-controller@4800c0 {
133 			compatible = "brcm,bcm63138-pmb";
134 			reg = <0x4800c0 0x10>;
135 			#reset-cells = <2>;
138 		pmb1: reset-controller@4800e0 {
139 			compatible = "brcm,bcm63138-pmb";
140 			reg = <0x4800e0 0x10>;
141 			#reset-cells = <2>;
145 			compatible = "brcm,bcm63138-ahci", "brcm,sata3-ahci";
146 			reg-names = "ahci", "top-ctrl";
147 			reg = <0xa000 0x9ac>, <0x8040 0x24>;
149 			#address-cells = <1>;
150 			#size-cells = <0>;
152 			reset-names = "ahci";
155 			sata0: sata-port@0 {
156 				reg = <0>;
161 		sata_phy: sata-phy@8100 {
162 			compatible = "brcm,bcm63138-sata-phy", "brcm,phy-sata3";
163 			reg = <0x8100 0x1e00>;
164 			reg-names = "phy";
165 			#address-cells = <1>;
166 			#size-cells = <0>;
169 			sata_phy0: sata-phy@0 {
170 				reg = <0>;
171 				#phy-cells = <0>;
178 		compatible = "simple-bus";
179 		#address-cells = <1>;
180 		#size-cells = <1>;
184 			compatible = "brcm,bcm6328-timer", "syscon";
185 			reg = <0x80 0x3c>;
189 			compatible = "brcm,bcm6345-uart";
190 			reg = <0x600 0x1b>;
193 			clock-names = "periph";
198 			compatible = "brcm,bcm6345-uart";
199 			reg = <0x620 0x1b>;
202 			clock-names = "periph";
207 			#address-cells = <1>;
208 			#size-cells = <0>;
209 			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand";
210 			reg = <0x2000 0x600>, <0xf0 0x10>;
211 			reg-names = "nand", "nand-int-base";
214 			interrupt-names = "nand";
218 			compatible = "brcm,bcm63138-bootlut";
219 			reg = <0x8000 0x50>;
223 			compatible = "syscon-reboot";